2

ICS97U877

0792A—04/15/04

Pin Descriptions

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levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.

ICS97U877 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential

pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC).

The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the

LVCMOS program pins (OE, OS) and the Analog Power input (AVDD).When OE is low, the outputs (except FB_OUTT/

FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a

the PLL is turned off and bypassed for test purposes.

When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic

detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform

a low power state where all outputs, the feedback and the PLL are OFF.When the inputs transition from both being logic

low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL

will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC)

The PLL in ICS97U877 clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,

FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]).ICS97U877

is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.

ICS97U877 is characterized for operation from 0°C to 70°C.