6

ICS97U877

0792A—04/15/04

Notes:

1.

Switching characteristics guaranteed for application frequency range.

2.

Static phase offset shifted by design.

Timing Requirements

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Max clock frequency

1.8V+0.1V @ 25°C

95

370

MHz

Application Frequency Range

1.8V+0.1V @ 25°C

160

350

MHz

Input clock duty cycle

40

60

%

CLK stabilization

15

µs

Switching Characteristics

1

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Output enable time

OE to any output

4.73

8

ns

Output disable time

OE to any output

5.82

8

ns

Period jitter

-30

30

ps

Half-period jitter

-60

60

ps

Input Clock

1

2.5

4

v/ns

Output Enable (OE), (OS)

0.5

v/ns

Output clock slew rate

SLr1(o)

1.5

2.5

3

v/ns

040

ps

0

-40

ps

Dynamic Phase Offset

-20

20

ps

Static Phase Offset

2

-50

0

50

ps

Output to Output Skew

40

ps

SSC modulation frequency

30.00

33

kHz

SSC clock input frequency

deviation

0.00

-0.50

%

PLL Loop bandwidth (-3 dB

from unity gain)

2.0

MHz

Cycle-to-cycle period jitter

Input slew rate

SLr1(i)