RT9834

3

DS9834-00 May 2013

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Copyright

2013 Richtek Technology Corporation. All rights reserved.

is a registered trademark of Richtek Technology Corporation.

Function Block Diagram

Timer

The Timer provides four kinds of delay time options

including 0ms, 55ms, 220ms, and 450ms.

VSET

The VSET generates a fixed threshold voltage.

CMP

Voltage Comparator which compares the voltage difference

between threshold voltage and VDD.

POR

Power on reset. It will set all digital logic to the right state

when power on.

Operation

When VDD is lower than threshold voltage set by VSET

circuit, the RESET output becomes high. If VDD remains

higher than the threshold voltage with a hysteresis voltage,

Timer will be active. After a specific delay time, the RESET

output becomes low. There is an internal pull-high resistor

connected to the MR pin. MR resets the RT9834 only

when it is pulled low. When MR releases and waits for a

delay time, output returns to its normal state related to

VDD. The RESET pin is a Pull-Push output, and it will

pull the output high to VDD, low to Ground. Adding a pull-

high resistor tied to any power which higher than VDD is

forbidden.

Timer

VSET

Threshold

Voltage Setting

POR

Power On Reset

CMP

N MOS

RESET/

RESET

VDD

VDD

P MOS

MR