MPC9443

MOTOROLA

TIMING SOLUTIONS

12

Figure 16. Output Duty Cycle (DC)

tF

tR

VCC=3.3V

VCC=2.5V

2.4

1.8V

0.55

0.6V

Figure 17. Output Transition Time test reference

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

VCC

VCCB2

GND

tP

T0

DC = tP/T0 x 100%

Figure 18. Cycle–to–cycle Jitter

Figure 19. Setup and hold time (tS, tH) test reference

The variation in cycle time of a signal between adjacent cycles,

over a random sample of adjacent cycle pairs

TN

TJIT(CC) = |TN–TN+1|

TN+1

VCC

VCCB2

GND

VCC

VCCB2

GND

tS

CCLK

PCLK

CLK_STOP

tH

Freescale Semiconductor, Inc.

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