MPC9443

TIMING SOLUTIONS

3

MOTOROLA

Table 1: Pin Configuration

Pin

I/O

Type

Function

CCLK

Input

LVCMOS

LVCMOS clock inputs

PCLK0, PCLK0

Input

LVCMOS

LVPECL differential clock input

PCLK1, PCLK1

Input

LVCMOS

LVPECL differential clock input

FSELA, FSELB, FSELC, FSELD

Input

LVCMOS

Output bank divide select input

CCLK_SEL

Input

LVCMOS

LVCMOS/LVPECL clock input select

PCLK_SEL

Input

LVCMOS

PCLK0/PCLK1 clock input select

OE0, OE1

Input

LVCMOS

Output tristate control

CLK_STOP

Input

LVCMOS

Synchronous output enable/disable (clock stop) control

GND

Supply

Negative voltage supply

VCCA, VCCB, VCCC, VCCD

Supply

Positive voltage supply output bank (VCC)

VCC

Supply

Positive voltage supply core (VCC)

QA0 to QA4

Output

LVCMOS

Bank A outputs

QB0 to QB2

Output

LVCMOS

Bank B outputs

QC0 to QC2

Output

LVCMOS

Bank C outputs

QD0 to QD4

Output

LVCMOS

Bank D outputs

Table 2: Supported Single and Dual Supply Configurations

Supply voltage

configuration

VCCa

VCCAb

VCCBc

VCCCd

VCCDe

GND

3.3V supply

3.3V

3.3V

3.3V

3.3V

3.3V

0 V

Mixed mode supply

3.3V

3.3V or 2.5V

3.3V or 2.5V

3.3V or 2.5V

3.3V or 2.5V

0 V

2.5V supply

2.5V

2.5V

2.5V

2.5V

2.5V

0 V

a.

VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels

b.

VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels

c.

VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels

d.

VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels

e.

VCCD is the positive power supply of the bank D outputs. VCCD voltage defines bank D output levels

Table 3: Function Table (Controls)

Control

Default

0

1

CCLK_SEL

0

PCLK or PCLK1 active (LVPECL clock mode)

CCLK active (LVCMOS clock mode)

PCLK_SEL

0

PCLK0 active, PCLK1 inactive

PCLK1 active, PCLK0 inactive

FSELA

0

fQA0:4 = fREF

fQA0:4 = fREF ÷ 2

FSELB

0

fQB0:2 = fREF

fQB0:2 = fREF ÷ 2

FSELC

0

fQC0:2 = fREF

fQC0:2 = fREF ÷ 2

FSELD

0

fQD0:4 = fREF

fQD0:4 = fREF ÷ 2

CLK_STOP

0

Normal operation

Outputs are synchronously disabled (stopped) in logic

low state

OE0, OE1

00

Asynchronous output enable control. See Table 4. OEN

Freescale Semiconductor, Inc.

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