EC24C02A/04A/08A/16A

2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM

Page 4 of 18

5H06N-Rev.F004

Available package types

Part Number

SOP-8

TSSOP-8

DFN-8

SOT23-5

MSOP-8

PDIP-8

EC24C02A

V

V

V

V

V

V

EC24C04A

V

V

V

V

V

V

EC24C08A

V

V

V

V

V

V

EC24C16A

V

V

V

--

V

V

Marking Information

Package type

Part Number

Marking

Marking Information

PDIP-8

EC24CXXANP1GX

24CXXA

LLLLL

YYWWT

XX is the memory of production.

LLLLL is the last five numbers of wafer lot number

YYWW is Date Code.

T is tracking Code ,T=X

SOP-8

EC24CXXANM1GX

TSSOP-8

EC24CXXANE1GX

MSOP-8

EC24CXXANR1GX

SOT23-5

EC24CXXANB2GX

24CXXA

LLLLL

XX is the memory of production.

LLLLL is the last five numbers of wafer lot number

DFN-8

EC24CXXANF2GX

CXXA

LLLL

XX is the memory of production.

LLLL is the last four numbers of wafer lot number

Memory Organization

EC24C02A, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an

8-bit data word address for random word addressing.

EC24C04A, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a

9-bit data word address for random word addressing.

EC24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a

10-bit data word address for random word addressing.

EC24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires

an 11-bit data word address for random word addressing.

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the

SDA pin may change only during SCL low time periods (see to Figure 1). Data changes during SCL high

periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede

any other command (see to Figure 2).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence,

the stop command will place the EEPROM in a standby power mode (see to Figure 2).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit

words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the

ninth clock cycle (see to Figure 3).