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4

Pin Descriptions

Pin

Name

I/O

Typ

Description

1

AUX IN

I

A

Auxiliary analog input.

2

AGND

P

Analog ground return.

3

V IN

I

A

Analog input. AC-couple input signal through a 0.1

µF capacitor.

4

AGND

P

Analog ground return.

5AV+

P

+3 Volt power supply for the analog circuits. Bypass each supply pin with 0.1

µF and

10

µF capacitors in parallel.

6

ACLP

I

D

Analog clamp switch.

7

RESET

I

D

Active-high master reset. Float pin when function not being used.

8AV+

P

+3 Volt power supply for the analog circuits. Bypass each supply pin with 0.1

µF and

10

µF capacitors in parallel.

9

DGND

P

Digital ground return.

10

DGND

P

Digital ground return.

11

DV+

P

+3 Volt power supply for the digital circuits. Bypass each supply pin with 0.1

µF and 10µF

capacitors in parallel.

12

CLK

I

D

18 MHz clock input.

13

SHP

I

D

Correlated double sampler reset voltage clamp override. Programmable active-high or

active-low through serial interface. Connect to +3 Volt digital supply when function not

being used (register values in default condition).

14

SHD

I

D

Correlated double sampler video signal voltage sample override. Programmable active-

high or active-low through serial interface. Connect to +3 Volt digital supply when func-

tion not being used (register values in default condition).

15

BOL

I

D

Active-high beginning of line switch input. Hold high during entire line of effective pixels.

Hold low during blanking period.

16

BLKCLP

I

D

Active-high black level clamp switch input. Pulse high during black pixels to set black

pixel level to the value stored in Output Black Level register. (See page 15.)

17

VREFP

IO

A

Top of DAC reference ladder. Normally bypassed with a 0.1

µF capacitor. An external

DAC reference voltage may be applied to this pin.

18

VREFN

IO

A

Bottom of DAC reference ladder. Normally bypassed with a 0.1

µF capacitor. An exter-

nal DAC reference voltage may be applied to this pin. Alternately, an external pull-down

resistor may be used to extend the DAC range. (See section 3.0).

19

VREFB

IO

A

Bottom of ADC reference ladder. Normally bypassed with a 0.1

µF capacitor and 10µF

capacitors in parallel. An external ADC reference voltage may be applied to this pin.

20

/CE

I

D

Active-low chip enable for the serial interface.

21

SCLK

I

D

Serial interface clock used to decode the serial input data.

22

SI DATA

I

D

Serial interface input port.

23

SO DATA

O

D

Serial interface output port.

24

DGND I/O

P

Digital output driver ground return.

25

DV+ I/O

P

+3 Volt power supply for the digital output driver circuits. Bypass each supply pin with

0.1

µF and 10µF capacitors in parallel.

26

D0

O

D

Digital output. Bit 0 of 9 (LSB) of the digital video output bus.

27

D1

O

D

Digital output. Bit 1 of 9 of the digital video output bus.

28

D2

O

D

Digital output. Bit 2 of 9 of the digital video output bus.

29

D3

O

D

Digital output. Bit 3 of 9 of the digital video output bus.

30

D4

O

D

Digital output. Bit 4 of 9 of the digital video output bus.

31

D5

O

D

Digital output. Bit 5 of 9 of the digital video output bus.

32

D6

O

D

Digital output. Bit 6 of 9 of the digital video output bus.