LM98503 datasheet(16/25 Pages) NSC

16 / 25 page

www.national.com

System Overview (continued)

configuration will then contain four 2-bit numbers indicating the

registers where the gain and offset values are located for a

maximum of four colors on each CFA line. In addition, the CFA

definition register will contain two 2-bit numbers that designate

the number of elements used in each CFA line for the particular

CFA pattern being applied to the system.

Example A contains a CFA pattern that repeats the colors cyan

and magenta on the first line, and repeats the pattern blue,

green, green, blue on the second line. Each 2-bit number in the

CFA line registers refers to a common set of PGA gain and

offset registers for each color. The first line indicates that the

color magenta uses the gain and offset values stored in PGA

gain register 1 (address 1h) and analog offset register 1

(address 5h). Also, the first line indicates that the color cyan

uses the gain and offset values in PGA gain register 2 (address

2h) and analog offset register 2 (address 6h). The second line

indicates gain and offset values for the color blue and the color

green in the same fashion as the first line.

In addition to specifying the gain and offset for each line, it is

also necessary to specify the number of elements contained in

each CFA line’s pixel pattern. The CFA definition register is used

to store this value (number of elements per line). In example A,

the user has stored the 2-bit binary number 01 into the CFA

definition register’s two LSB’s indicating that the pattern in line 0

contains two repeating colors or elements. Also, the 2-bit binary

number 11 has been written into bit 2 and bit 3 of the CFA

definition register indicating that the respective CFA pattern

contains four repeating colors or elements, as the colors blue

and green alternate position in the example pattern.

Once both lines for the pattern have been stored, it is applied

when the beginning of line (BOL) signal is asserted by the user.

One line of the CFA pattern is applied repeatedly until the BOL

signal is reset (at the end of the current line). Once the BOL

signal is set again, the CFA line information is changed from that

defined by the CFA line 0 register to that defined by the CFA line

1 register and the process starts again. For more details of the

timing of the BOL signal, please refer to Figure 6.

1.11 Software Control

There are two software control registers accessible via the serial

interface.

The software control registers are divided into

customer (register 0) and advanced (register 1) functions.

Please refer to the register data descriptions for more

information on the software control registers.

1.12 Power Level Control

The LM98503 is equipped with two power trim registers that

may be used to adjust power levels of various circuits internal to

the device. In its default condition, the LM98503 is set for

optimum power and performance, and modifying the values

stored in the power level control registers will affect performance

as a result of the change in power level(s). In applications where

maximum performance is desired, the default values should be

used. Otherwise, power levels may be decreased at the slight

expense of performance. Please refer to the register data

descriptions for more information regarding the power level

control registers.

The ADC coarse and fine bank power adjustment bits are

located in the power level control 2 register, bits 7:4. Altering

these bits may significantly affect performance and power

dissipation. Please see ’DNL vs. Power Control Setting @

18MHz Clock Frequency’ and ’Power Dissipation vs. Power

Control Setting’ on page ’13.

Example A

CFA Line 0

CFA Line 1

CFA Definition

LM98503 Datasheet(PDF) 16 Page - National Semiconductor (TI)

LM98503 Datasheet(HTML) 16 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Datasheet Download

Link URL