AD9695 datasheet(89/136 Pages) AD

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AD9695

Data Sheet

Rev. 0 | Page 88 of 135

LATENCY

END TO END TOTAL LATENCY

Total latency in the AD9695 is dependent on the chip

application mode and the JESD204B configuration. For any

given combination of these parameters, the latency is

deterministic, however, the value of this deterministic latency

must be calculated as described in the Example Latency

Calculations section.

Table 38 shows the combined latency through the ADC and

DSP for the different chip application modes supported by the

AD9695. Table 37 shows the latency through the JESD204B

block for each application mode based on the M/L ratio. For

both tables, latency is typical and is in units of the encode clock.

The latency through the JESD204B block does not depend on

the output data type (real or complex). Therefore, data type is

not included in Table 37.

To determine the total latency, select the appropriate ADC + DSP

latency from Table 34 and add it to the appropriate JESD204B

latency from Table 35. Example calculations are provided in the

following section.

EXAMPLE LATENCY CALCULATIONS

Example Configuration 1 is as follows:



ADC application mode = full bandwidth



Real outputs



L = 4, M = 2, F = 1, S = 1 (JESD204B mode)



M/L = 0.5



Latency = 31 + 25 = 56 encode clocks

Example Configuration 2 is as follows:



ADC application mode = DCM4



Complex outputs



L = 2, M = 2, F = 2, S = 1 (JESD204B mode)



M/L = 1



Latency = 162 + 50 = 212 encode clocks

LMFC REFERENCED LATENCY

Some FPGA vendors may require the end user to know LMFC

referenced latency to make appropriate deterministic latency

adjustments. If they are required, the latency values in Table 38

and Table 39 can be used for the analog input to LMFC and

LMFC to data output latency values, respectively.

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