AD9695 datasheet(95/136 Pages) AD

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AD9695

Data Sheet

Rev. 0 | Page 94 of 135

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit

locations. The memory map is divided into the following

sections:



Analog Devices SPI registers (Register 0x0000 to



Clock/SYSREF/chip power-down pin control registers

(Register 0x003F to Register 0x0201)



Fast detect and signal monitor control registers

(Register 0x0245 to Register 0x027A)



DDC function registers (Register 0x0300 to



Digital outputs and test modes registers (Register 0x0550 to



Programmable filter control and coefficients registers

(Register 0x0DF8 to Register 0x0F7F)



VREF/analog input control registers (Register 0x18A6 to

Table 47 (see the Memory Map Register Details section)

documents the default hexadecimal value for each hexadecimal

address shown. The column with the heading Bit 7 (MSB) is the

start of the default hexadecimal value given. For example,

Address 0x0561, the output sample mode register, has a

hexadecimal default value of 0x01, which means that Bit 0 = 1,

and the remaining bits are 0s. This setting is the default output

format value, which is twos complement. For more information

on this function and others, see Table 47.

Open and Reserved Locations

All address and bit locations that are not included in Table 47

are not currently supported for this device. Write unused bits

of a valid address location with 0s unless the default value is

set otherwise. Writing to these locations is required only when

part of an address location is unassigned (for example,

Address 0x0561). If the entire address location is open (for

example, Address 0x0013), do not write to this address location.

Default Values

After the AD9695 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table, Table 47.

Logic Levels

An explanation of logic level terminology follows:



“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”



“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”



X denotes a don’t care bit.

Channel Specific Registers

Some channel setup functions, such as the input buffer control

value for each channel. In these cases, channel address locations

are internally duplicated for each channel. These registers and

bits are designated in Table 47 as local. These local registers and

bits can be accessed by setting the appropriate Channel A or

Channel B bits in Register 0x0008. If both bits are set, the

subsequent write affects the registers of both channels. In a read

cycle, set only Channel A or Channel B to read one of the two

registers. If both bits are set during an SPI read cycle, the device

returns the value for Channel A. Registers and bits designated as

global in Table 47 affect the entire device and the channel

features for which independent settings are not allowed

between channels. The settings in Register 0x0005 do not affect

the global registers and bits.

SPI Soft Reset

After issuing a soft reset by programming 0x81 to Register 0x0000,

the AD9695 requires 5 ms to recover. When programming the

AD9695 for application setup, ensure that an adequate delay is

programmed into the firmware after asserting the soft reset and

before starting the device setup.

AD9695 Datasheet(PDF) 95 Page - Analog Devices

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