AD9695 datasheet(97/136 Pages) AD

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AD9695

Data Sheet

Rev. 0 | Page 96 of 135

Address

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x0006

Chip grade

[7:4]

Chip speed grade

Chip speed grade.

0x0

0x00

625 MSPS.

0x01

1300 MSPS.

[3:0]

Reserved

Reserved.

DNC

0x0008

Device index

[7:2]

Reserved

Reserved.

0x0

Channel B

ADC Core B does not receive the next

SPI command.

0x1

R/W

ADC Core B receives the next SPI

command.

Channel A

ADC Core A does not receive the next

SPI command.

0x1

R/W

ADC Core A receives the next SPI

command.

0x000A

Scratch pad

[7:0]

Scratch pad

Chip scratch pad register. This register

provides a consistent memory

location for software debug.

0x0

R/W

0x000B

SPI revision

[7:0]

SPI revision

SPI revision register.

0x1

0x01

Revision 1.0.

00000001

Revision 1.0.

0x000C

Vendor ID LSB

[7:0]

Vendor ID [7:0].

0x56

0x000D

Vendor ID MSB

[7:0]

Vendor ID [15:8].

0x04

0x000F

Transfer

[7:1]

Reserved

Reserved.

0x0

Chip transfer

Self clearing chip transfer bit. This bit

is used to update the DDC phase

increment and phase offset registers

when the DDC phase update mode bit

(Register 0x0300, Bit 7) = 1. This setting

makes it possible to synchronously

update the DDC mixer frequencies. It

is also used to update the coefficients

for the programmable filter (PFILT).

0x0

R/W

Do nothing. This bit it is only cleared

after the transfer completes.

Self clearing bit used to synchronize

the transfer of data from master to

slave registers.

Clock/SYSREF/Chip Power-Down Pin Control Registers

0x003F

Chip power-

down pin (local)

Local chip power-

down pin disable

Function is determined by

0x0

R/W

Power-down pin (PDWN/STBY)

enabled (default).

Power-down pin (PDWN/STBY)

disabled/ignored.

[6:0]

Reserved

Reserved.

0x0

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