AD7902 datasheet(15/29 Pages) AD

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AD7902

Data Sheet

Rev. B | Page 14 of 28

THEORY OF OPERATION

Figure 31. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7902 is a fast, low power, precise, dual 16-bit ADC

using a successive approximation architecture.

The AD7902 is capable of simultaneously converting 1,000,000

samples per second (1 MSPS) and powers down between con-

versions. When operating at 10 kSPS, for example, it typically

consumes 70 µW per ADC, making it ideal for battery-powered

applications.

The AD7902 provides the user with an on-chip track-and-hold

and does not exhibit any pipeline delay or latency, making it

ideal for multichannel multiplexed applications.

The AD7902 can be interfaced to any 1.8 V to 5 V digital logic

family. It is available in a 20-lead QSOP that allows for flexible

configurations. The device is pin-for-pin compatible with the

differential, 16-bit AD7903.

CONVERTER OPERATION

The AD7902 is a dual successive approximation ADC based on

a charge redistribution DAC. Figure 31 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 16 binary-weighted capacitors, which are

connected to the two comparator inputs.

During the acquisition phase of each ADC, terminals of the array

tied to the input of the comparator are connected to GND via

the switches, SWx+ and SWx−. All independent switches are

connected to the analog inputs. Therefore, the capacitor arrays are

used as sampling capacitors and acquire the analog signal on the

INx+ and INx− inputs. When the acquisition phase is complete

and the CNVx input goes high, a conversion phase is initiated.

When the conversion phase begins, SWx+ and SWx− are opened

first. The two capacitor arrays are then disconnected from the

inputs and connected to the GND input. Therefore, the

differential voltage between the INx+ and INx− inputs,

captured at the end of the acquisition phase, is applied to the

comparator inputs, causing the comparator to become

unbalanced. By switching each element of the capacitor array

between GND and REFx, the comparator input varies by

binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/65,536).

The control logic toggles these switches, starting with the MSB,

to bring the comparator back into a balanced condition. After the

completion of this process, the device returns to the acquisition

phase, and the control logic generates the ADC output code and

a busy signal indicator.

Because the AD7902 has an on-board conversion clock, the

serial clock, SCKx, is not required for the conversion process.

Transfer Functions

The ideal transfer characteristic for the AD7902 is shown in

Figure 32 and Table 7.

Figure 32. ADC Ideal Transfer Function

Table 7. Output Codes and Ideal Input Voltages

Description

Analog Input,

VREF = 5V

Digital Output

Code (Hex)

FSR − 1 LSB

4.999924 V

FFFF1

Midscale + 1 LSB

2.500076 V

8001

Midscale

2.5 V

8000

Midscale − 1 LSB

2.499924 V

7FFF

−FSR + 1 LSB

76.3 µV

0001

−FSR

0 V

00002

1 This is also the code for an overranged analog input (V

IN+ − VIN− above VREF − VGND).

2 This is also the code for an underranged analog input (V

IN+ − VIN− below VGND).

COMP

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNVx

CONTROL

LOGIC

SWx+

LSB

SWx–

LSB

INx+

REFx

GND

INx–

MSB

16,384C

32,768C

16,384C

32,768C

000 ... 000

000 ... 001

000 ... 010

111 ... 101

111 ... 110

111 ... 111

–FSR

–FSR + 1 LSB

–FSR + 0.5 LSB

+FSR – 1 LSB

+FSR – 1.5 LSB

ANALOG INPUT

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