TMS44100, TMS44100P, TMS46100, TMS46100P

4194304-WORD BY 1-BIT

DYNAMIC RANDOM-ACCESS MEMORIES

SMHS561A – MARCH 1995 – REVISED JUNE 1995

4

POST OFFICE BOX 1443

refresh

A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x100P) to retain data. This

can be achieved by strobing each of the 1024 rows (A0 – A9). A normal read or write cycle refreshes all bits in

each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,

conserving power as the output buffer remains in the high-impedance state. Externally generated addresses

must be used for a RAS-only refresh. Hidden refresh can be performed while maintaining valid data at the

precharge period, similar to a RAS-only refresh cycle. The external address is ignored during the hidden-refresh

cycle.

CAS-before-RAS (CBR) refresh

external address is ignored and the refresh address is generated internally.

A low-power battery-backup refresh mode that requires less than 300-

µA (TMS46100P) or 500-µA

(TMS44100P) refresh current is available on the low-power devices. Data integrity is maintained using CBR

refresh with a period of 125

µs while holding RAS low for less than 1 µs. To minimize current consumption, all

self refresh

The self-refresh mode is entered by dropping CAS low prior to RAS going low. CAS and RAS are both held low

for a minimum of 100

µs. The chip is then refreshed by an on-board oscillator. No external address is required

because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS

addresses) must be executed before continuing with normal operation. This ensures the DRAM is fully

refreshed.

power up

To achieve proper device operation, an initial pause of 200

µs followed by a minimum of eight initialization cycles

(RAS-only or CBR) cycle.

test mode

An industry-standard design-for-test (DFT) mode is incorporated in the TMS4x100 and TMS4x100P. A CBR

cycle with W low (WCBR) cycle is used to enter the test mode. In the test mode, data is written into and read

from eight sections of the array in parallel. Data is compared upon reading and if all bits are equal, the data-out

terminal goes high. If any one bit is different, the data-out terminal goes low. Any combination of read, write,

read-write, or page-mode cycles can be used in the test mode. The test-mode function reduces test times by

enabling the 4-Mbit DRAM to be tested as if it were a 512K DRAM, where row address 10, column address 10,

and column address 0 are not used. A RAS-only or CBR refresh cycle is used to exit the DFT mode.