TMS44100, TMS44100P, TMS46100, TMS46100P

4194304-WORD BY 1-BIT

DYNAMIC RANDOM-ACCESS MEMORIES

SMHS561A – MARCH 1995 – REVISED JUNE 1995

1

POST OFFICE BOX 1443

(

±10% Tolerance)

(

±10% Tolerance)

– 200-

µA CMOS Standby

– 200-

µA Self Refresh

– 300-

µA Extended-Refresh Battery

Backup

ACCESS ACCESS ACCESS

READ

TIME

TIME

TIME

OR WRITE

(tRAC)(tCAC)(tAA)

CYCLE

(MAX)

(MAX)

(MAX)

(MIN)

’4x100/P-60

60 ns

15 ns

30 ns

110 ns

’4x100/P-70

70 ns

18 ns

35 ns

130 ns

’4x100/P-80

80 ns

20 ns

40 ns

150 ns

Memory Access

– 1024-Cycle Refresh in 16 ms

– 128 ms (Max) for Low-Power,

Self-Refresh Version ( TMS4x100P)

0

°C to 70°C

DEVICE

POWER

SUPPLY

SELF-REFRESH

BATTERY

BACKUP

REFRESH

CYCLES

TMS44100

5 V

—

1024 in 16 ms

TMS44100P

5 V

YES

1024 in 128 ms

TMS46100

3.3 V

—

1024 in 16 ms

TMS46100P

3.3 V

YES

1024 in 128 ms

These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines

are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility.

The TMS4x100 and TMS4x100P are offered in a 20- / 26-lead plastic surface-mount small-outline ( TSOP)

package (DGA suffix) and a 300-mil 20- / 26-lead plastic surface-mount SOJ package (DJ suffix). Both packages

are characterized for operation from 0

°C to 70°C.

ADVANCE INFORMATION concerns new products in the sampling or

preproduction phase of development. Characteristic data and other

specifications are subject to change without notice.

PIN NOMENCLATURE

A0 – A10

Address Inputs

CAS

Column-Address Strobe

D

Data In

NC

No Connection

Q

Data Out

RAS

Row-Address Strobe

W

Write Enable

VCC

5-V or 3.3-V Supply

VSS

Ground

DJ PACKAGE

( TOP VIEW )

Q

CAS

NC

A9

A8

A7

A6

A5

A4

26

25

24

23

22

18

17

16

15

14

1

2

3

4

5

9

10

11

12

13

DGA PACKAGE

( TOP VIEW )

D

W

RAS

NC

A10

A0

A1

A2

A3

Q

CAS

NC

A9

A8

A7

A6

A5

A4

26

25

24

23

22

18

17

16

15

14

1

2

3

4

5

9

10

11

12

13

D

W

RAS

NC

A10

A0

A1

A2

A3

EPIC is a trademark of Texas Instruments Incorporated.

description

The

TMS4x100

series

are

high-speed,

4 194 304-bit dynamic random-access memories,

organized as 4 194 304 words of one bit each. The

TMS4x100P series are high-speed, low-power,

self-refresh with extended-refresh, 4 194 304-bit

dynamic random-access memories, organized as

4 194 304 words of one bit each. Both series

employ

state-of-the-art

EPIC

Performance Implanted CMOS) technology for

high performance, reliability, and low voltage.

Copyright

© 1995, Texas Instruments Incorporated