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AD9642

Data Sheet

Rev. B | Page 6 of 28

SWITCHING SPECIFICATIONS

Table 4.

AD9642-170

AD9642-210

AD9642-250

Parameter

Temp

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

625

MHz

Conversion Rate1

Full

170

210

250

MSPS

CLK Period—Divide-by-1 Mode (tCLK)

Full

5.8

4.8

CLK Pulse Width High (tCH)

Divide-by-1 Mode, DCS Enabled

Full

2.61

2.9

3.19

2.16

2.4

2.64

1.8

2.0

2.2

Divide-by-1 Mode, DCS Disabled

Full

2.76

2.9

3.05

2.28

2.4

2.52

1.9

2.0

2.1

Divide-by-2 Mode Through

Divide-by-8 Mode

Full

0.8

Aperture Delay (tA)

Full

1.0

Aperture Uncertainty (Jitter, tJ)

Full

0.1

ps rms

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD)

Full

4.1

4.7

5.2

4.1

4.7

5.2

4.1

4.7

5.2

DCO Propagation Delay (tDCO)

Full

4.7

5.3

5.8

4.7

5.3

5.8

4.7

5.3

5.8

DCO-to-Data Skew (tSKEW)

Full

0.3

0.5

0.7

0.3

0.5

0.7

0.3

0.5

0.7

Pipeline Delay (Latency)

Full

Cycles

Wake-Up Time (from Standby)

Full

μs

Wake-Up Time (from Power-Down)

Full

100

μs

Out-of-Range Recovery Time

Full

Cycles

1 Conversion rate is the clock rate after the divider.

Timing Diagram

VIN

CLK+

CLK–

DCO–

DCO+

D0±/D1±

(LSB)

EVEN/ODD

D12±/D13±

(MSB)

N – 10

N – 9

N – 8

N – 7

N – 6

D12

N – 10

D13

N – 10

D12

N – 9

D13

N – 9

D12

N – 8

D13

N – 8

D12

N – 7

D12

N – 7

D12

N – 6

N – 1

N + 1

N + 2

N + 3

N + 4

N + 5

tCH

tPD

tSKEW

tDCO

tCLK

Figure 2. LVDS Data Output Timing

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