Data Sheet

AD9642

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 13 are not currently supported for this device.

Table 13. Memory Map Registers

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default

Notes/

Comments

Chip Configuration Registers

0x00

SPI port

configuration

0

LSB first

Soft reset

1

1

Soft reset

LSB first

0

0x18

Nibbles

are mirrored

so that LSB

first mode

or MSB first

mode is set

correctly,

regardless

of shift

mode.

0x01

Chip ID

8-bit chip ID[7:0]

(AD9642 = 0x86)

(default)

0x86

Read only.

0x02

Chip grade

Open

Open

Speed grade ID

00 = 250 MSPS

01 = 210 MSPS

11 = 170 MSPS

Open

Open

Open

Open

Speed

grade ID

used to

differentiate

devices;

read only.

Transfer Register

0xFF

Transfer

Open

Open

Open

Open

Open

Open

Open

Transfer

0x00

Synchro-

nously

transfers

data from

the master

shift register

to the slave.

ADC Functions Registers

0x08

Power modes

Open

Open

Open

Open

Open

Open

Internal power-down mode

00 = normal operation

01 = full power-down

10 = standby

11 = reserved

0x00

Determines

various

generic

modes

of chip

operation.

0x09

Global clock

Open

Open

Open

Open

Open

Open

Open

Duty cycle

stabilizer

(default)

0x01

0x0B

Clock divide

Open

Open

Input clock divider phase adjust

000 = no delay

001 = 1 input clock cycle

010 = 2 input clock cycles

011 = 3 input clock cycles

100 = 4 input clock cycles

101 = 5 input clock cycles

110 = 6 input clock cycles

111 = 7 input clock cycles

Clock divide ratio

000 = divide by 1

001 = divide by 2

010 = divide by 3

011 = divide by 4

100 = divide by 5

101 = divide by 6

110 = divide by 7

111 = divide by 8

0x00

Clock

divide

values

other than

000 auto-

matically

cause the

duty cycle

stabilizer to

become

active.

0x0D

Test mode

User test

mode

control

0 = con-

tinuous/

repeat

pattern

1 = single

pattern,

then 0s

Open

ResetPN

longgen

Reset PN

short gen

Output test mode

0000 = off (default)

0001 = midscale short

0010 = positive FS

0011 = negative FS

0100 = alternating checkerboard

0101 = PN long sequence

0110 = PN short sequence

0111 = one/zero word toggle

1000 = user test mode

1001 to 1110 = unused

1111 = ramp output

0x00

When this

register is

set, the test

data is

placed on

the output

pins in place

of normal

data.

Rev. B | Page 25 of 28