T0534VL datasheet(4/9 Pages) CITC

4 / 9 page

Application Information

Pin Connection in PCB

T0534VL is capable to provide ESD protection for

four data lines simultaneously. The pin connection is

shown in Figure 1.

Four parallel data lines, from inner IC to I/O port

connector, could connect to

four I/O pins

directly. Pin 2 of

is the negative reference

pin, which should connect to the GND of PCB. The

connection wires should be as short as possible in

order to minimize the parasitic inductance.

I/O1

I/O2

GND

To Inner IC

VCC

To Connector

I/O3

I/O4

To Inner IC

To Connector

Figure 1 T05

34VL pin connection in PCB

PCB Layout Guidelines

For optimum ESD protection and the whole circuit

performance, the following PCB layout guidelines are

recommended:

GND pin to the PCB GND rail path

should be as short as possible. It could reduce the

ESD transient return path to GND.

The vias connecting

VCC & GND pins

to the PCB VCC & GND should be wide.

Place

as close to the connector port as

possible. It could reduce the parasitic inductance

and restrict ESD coupling into adjacent traces.

Avoid running critical signals near board edges.

Figure 2 T05

34VL Layout Guideline

Universal Serial Bus ESD Protection

USB

Controller

VBUS

D+

D-

GND

VBUS

D+

D-

GND

USB

Port1

USB

Port2

GND

T0534VL

T05

34VL

T05

34VL

T0534VL

Chip Integration Technology Corporation

Low Capacitance ESD Protection Device

T0534VL

□

Document ID : DS-22V21

Revised Date : 2017/07/20

Revision : C

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