AD7626 datasheet(25/30 Pages) AD

25 / 30 page

AD7626

Data Sheet

Rev. D | Page 24 of 29

Self Clocked Mode

The digital operation of the AD7626 in self clocked interface

mode is shown in Figure 42. This interface mode reduces the

number of traces between the ADC and the digital host to two

LVDS pairs (CLK± and D±) or to a single pair if sharing a

common CLK±. Multiple AD7626 devices can share a common

CLK± signal. This can be useful in reducing the number of

LVDS connections to the digital host.

When the self clocked interface mode is used, each ADC data-

word is preceded by a 010 sequence. The first zero is automatically

on D± once tMSB has elapsed. The 2-bit header is then clocked

out by the first two CLK± falling edges. This header synchronizes

D± of each conversion in the digital host because, in this mode,

there is no data clock output synchronous to the data (D±) to

allow the digital host to acquire the data output.

Synchronization of the D± data to the digital host acquisition

clock is accomplished by using one state machine per AD7626

device. For example, using a state machine that runs at the

same speed as CLK± incorporates three phases of this clock

frequency (120º apart). Each phase acquires the data D± as

output by the ADC.

The AD7626 data captured on each phase of the state machine

clock is then compared. The location of the 1 in the header in each

set of data acquired allows the user to choose the state machine

clock phase that occurs during the data valid window of D±.

The self clocked mode data capture method allows the digital host

to adapt the result capture timing to accommodate variations in

propagation delay through any AD7626, as, for example, where

data is captured from multiple AD7626s sharing a common

input clock.

Conversions are initiated by a CNV± pulse. The CNV± pulse

must be returned low (tCNVH maximum) for valid operation. After

a conversion begins, it continues until completion. Additional

CNV± pulses are ignored during the conversion phase. After

the time, tMSB, elapses, the host begins to burst the CLK± signal

to the AD7626. All 18 CLK± pulses are to be applied in the time

window framed by tMSB and the subsequent tCLKL. The required

18 CLK± pulses must finish before tCLKL (referenced to the next

conversion phase) elapses. Otherwise, the data is lost because it

is overwritten by the next conversion result.

Set CLK± to idle high between bursts of 18 CLK± pulses. The

header bit and conversion data of the next ADC result are output

on subsequent falling edges of CLK± during the next burst of

the CLK± signal.

CLK+

tCLKL

D+

D–

CLK–

N – 1

ACQUISITION

tCLKD

tCLK

tMSB

D15

D14

D15

N + 1

tCYC

CNV+

tCNVH

SAMPLE N

SAMPLE N + 1

CNV–

Figure 42. Self Clocked Interface Mode Timing Diagram

AD7626 Datasheet(PDF) 25 Page - Analog Devices

AD7626 Datasheet(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Datasheet Download

Link URL