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AD9251 Datasheet(PDF) 12 Page - Analog Devices

Part # AD9251
Description  1.8 V Dual Analog-to-Digital Converter
PDF  37 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9251 Datasheet(HTML) 12 Page - Analog Devices

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Data Sheet
AD9251
Rev. A | Page 11 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK+
CLK–
SYNC
NC
NC
(LSB) D0B
D1B
D2B
D3B
DRVDD
D4B
D5B
D6B
D7B
D8B
D9B
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
ORA
D13A (MSB)
D12A
D11A
D10A
D9A
DRVDD
D8A
D7A
D6A
D5A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9251
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND
TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
Figure 5. Pin Configuration
Table 8. Pin Function Description
Pin No.
Mnemonic
Description
0
GND
Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND.
1, 2
CLK+, CLK−
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
3
SYNC
Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
4, 5, 25, 26
NC
Do Not Connect.
6 to 9, 11 to 18, 20, 21
D0B to D13B
Channel B Digital Outputs. D13B = MSB.
10, 19, 28, 37
DRVDD
Digital Output Driver Supply (1.8 V to 3.3 V).
22
ORB
Channel B Out-of-Range Digital Output.
23
DCOB
Channel B Data Clock Digital Output.
24
DCOA
Channel A Data Clock Digital Output.
27, 29 to 36, 38 to 42
D0A to D13A
Channel A Digital Outputs. D13A = MSB.
43
ORA
Channel A Out-of-Range Digital Output.
44
SDIO/DCS
SPI Data Input/Output (SDIO). Bidirectional SPI Data I/O in SPI mode. 30 kΩ internal pull-
down in SPI mode.
Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode.
30 kΩ internal pull-up in non-SPI (DCS) mode.
45
SCLK/DFS
SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down.
Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal
pull-down.
DFS high = twos complement output.
DFS low = offset binary output.
46
CSB
SPI Chip Select. Active low enable; 30 kΩ internal pull-up.
47
OEB
Digital Input. Enable Channel A and Channel B digital outputs if low, tristate outputs if high.
30 kΩ internal pull-down.
48
PDWN
Digital Input. 30 kΩ internal pull-down.
PDWN high = power-down device.
PDWN low = run device, normal operation.
49, 50, 53, 54, 59, 60, 63, 64
AVDD
1.8 V Analog Supply Pins.
51, 52
VIN+A, VIN−A
Channel A Analog Inputs.



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