AD9251

Data Sheet

Rev. B | Page 32 of 36

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 16 are not currently supported for this device.

Table 16.

Address

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Comments

Chip Configuration Registers

0x00

SPI port

configuration

(global)

0

LSB

first

Soft reset

1

1

Soft

reset

LSB first

0

0x18

The nibbles are

mirrored so

that LSB- or

MSB-first mode

registers

correctly,

regardless of

shift mode

0x01

Chip ID (global)

8-bit chip ID bits [7:0]

AD9251 = 0x23

Unique chip ID

used to diffe-

rentiate

devices; read

only

0x02

Chip grade

(global)

Open

Speed grade ID 6:4

20 MSPS = 000

40 MSPS = 001

65 MSPS = 010

80 MSPS = 011

Open

Unique speed

grade ID used

to differentiate

devices; read

only

Device Index and Transfer Registers

0x05

Channel index

Open

Open

Open

Open

Open

Open

ADC B

default

ADC A

default

0x03

Bits are set to

determine

which device

on chip

receives the

next write

command; the

default is all

devices on chip

0xFF

Transfer

Open

Open

Open

Open

Open

Open

Open

Transfer

0x00

Synchronously

transfers data

from the

master shift

register to the

slave

Program Registers (May or May Not Be Indexed by Device Index)

0x08

Modes

External

power-

down

enable

(local)

External pin function

0x00 full power-

down

0x01 standby

(local)

Open

Open

00 = chip run

01 = full power-

down

10 = standby

11 = chip wide

digital reset

(local)

0x80

Determines

various generic

modes of chip

operation

0x09

Clock (global)

Open

Open

Open

Open

Open

Duty

cycle

stabilize

0x00

0x0B

Clock divide

(global)

Open

Clock divider [2:0]

Clock divide ratio

000 = divide by 1

001 = divide by 2

010 = divide by 3

011 = divide by 4

100 = divide by 5

101 = divide by 6

110 = divide by 7

111 = divide by 8

0x00

The divide ratio

is the value

plus 1