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AD9262EBZ Datasheet(PDF) 20 Page - Analog Devices |
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AD9262EBZ Datasheet(HTML) 20 Page - Analog Devices |
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20 / 33 page  AD9262 Rev. A | Page 19 of 32 Internal PLL Clock Distribution The alternative clocking option available on the AD9262 is to apply a low frequency reference clock and use the on-chip clock multip- lier to generate the high frequency fMOD rate. The internal clock architecture is shown in Figure 53. PHASE DETECTOR DIVIDER PLL MULT 0x0A[5:0] CLK+/CLK– MODULATOR CLOCK 640MSPS PLLENABLE 0x09[2] LOOP FILTER VCO PLL ÷2 ÷N Figure 53. Internal Clock Architecture The clock multiplication circuit operates such that the VCO outputs a frequency, fVCO, equal to the reference clock input multiplied by N. fVCO = (CLK±) × (N) where N is the PLL multiplication (PLLMULT) factor. The Σ-Δ modulator clock frequency, fMOD, is equal to fMOD = fVCO ÷ 2 The reference clock, CLK±, is limited to 30 MHz to 160 MHz when configured to use the on-chip clock multiplier. Given the input range of the reference clock and the available multiplication factors, the fVCO is approximately 1280 MHz. This results in the desired fMOD rate of 640 MHz with a 50% duty cycle. Before the PLL enable register bit (PLLENABLE) is set, the PLL multiplication factor should be programmed into Register 0x0A[5:0]. After setting the PLLENABLE bit, the PLL locks and reports a locked state in Register 0x0A[7]. If the PLL multiplica- tion factor is changed, the PLL enable bit should be reset and set again. Some common clock multiplication factors are shown in Table 11. The recommended sequence for enabling and programming the on-chip clock multiplier is shown in Table 9. Table 9. Sequence for Enabling and Programming the PLL Step Procedure 1 Apply a reference clock to the CLK± pins. 2 Program the PLL multiplication factor in Register 0x0A[5:0]. See Table 10. 3 Enable the PLL; Register 0x09 = 04 (decimal). 4 Enable PLL autoband select. 5 Initiate an SRC reset; Register 0x101[5:0] = 0. 6 Set SRC to desired value via Register 0x101[5:0]. PLL Autoband Select The PLL VCO has a wide operating range that is covered by overlapping frequency bands. For any desired VCO output frequency, there are multiple valid PLL band select values. The AD9262 possesses an automatic PLL band select feature on chip that determines the optimal PLL band setting. This feature can be enabled by writing to Register 0x0A[6]and is the recommended configuration with the PLL clocking option. When the device is taken out of sleep or standby mode, Register 0x0A[6] must be toggled to reinitiate the autoband detect. See Table 9 for informa- tion about enabling the autoband select along with configuring the PLL. Table 10. PLL Multiplication Factors 0x0A[5:0] PLLMULT (N) 0x0A[5:0] PLLMULT (N) 1 8 33 32 2 8 34 34 3 8 35 34 4 8 36 34 5 8 37 34 6 8 38 34 7 8 39 34 8 8 40 34 9 9 41 34 10 10 42 42 11 10 43 42 12 12 44 42 13 12 45 42 14 14 46 42 15 15 47 42 16 16 48 42 17 17 49 42 18 18 50 42 19 18 51 42 20 20 52 42 21 21 53 42 22 21 54 42 23 21 55 42 24 24 56 42 25 25 57 42 26 25 58 42 27 25 59 42 28 28 60 42 29 28 61 42 30 30 62 42 31 30 63 42 32 32 64 42 |
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