AD9262EBZ datasheet(23/33 Pages) AD

23 / 33 page

AD9262

Rev. A | Page 22 of 32

Sample Rate Converter

The sample rate converter (SRC) allows the flexibility of a

user-defined output sample rate, enabling a more efficient

and direct interface to the digital receiver blocks.

The sample rate converter performs an interpolation and

resampling procedure to provide an output data rate of

20 MSPS to 168 MSPS. Table 16 and Table 17 detail the

coefficients for the INT1 and INT2 filters. The sinc filters

are a standard implementation.

The relationship between the output sample rate and the Σ-Δ

modulator clock rate is expressed as follows:

fOUT = fMOD ÷ KOUT

Table 18 shows the available KOUT conversion factors.

Table 16. INT1 Filter Coefficients

Coefficient

Number

Coefficient

Number

Coefficient

C0, C26

C7, C19

C1, C25

C8, C18

2450

C2, C24

−97

C9, C17

C3, C23

C10, C16

−5761

C4, C22

361

C11, C15

C5, C21

C12, C14

20,433

C6, C20

−1017

C13

32,768

Table 17. INT2 Filter Coefficients

Coefficient

Number

Coefficient

Number

Coefficient

C0, C14

−27

C4, C10

−1032

C1, C13

C5, C9

C2, C12

227

C6, C8

4928

C3, C11

8192

If the main clocking source of the AD9262 is provided by the

PLL, it is important, once the PLL has been programmed and

locked, to initiate an SRC reset before programming the desired

KOUT factor. This is done by first writing 0x101[5:0] = 0 and

then rewriting to the same register with the appropriate KOUT

value. In addition, if the AD9262 loses its clock source and then

later regains it, an SRC reset should be initiated.

Table 18. SRC Conversion Factors

0x101[5:0]

KOUT

0x101[5:0]

KOUT

0x101[5:0]

KOUT

SRC reset

11.5

22.5

12.5

23.5

13.5

24.5

14.5

25.5

4.5

15.5

26.5

5.5

16.5

27.5

6.5

17.5

28.5

7.5

18.5

29.5

8.5

19.5

30.5

9.5

20.5

31.5

10.5

21.5

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