CY2213
Document #: 38-07263 Rev. *E
Page 8 of 10
Figure 12 shows the definition of cycle-to-cycle duty cycle
error. Cycle-to-cycle duty cycle error is defined as the
difference between high-times of adjacent cycles over many
cycles (typically 12800 cycles at 400 MHz). Equal require-
ments apply to the low-times. tDC,ERR is defined as the clock
output cycle-to-cycle duty cycle error.
Figure 13 shows the definition of long-term jitter error.
Long-term jitter is defined as the accumulated timing error over
many cycles (typically 12800 cycles at 400 MHz). It applies to
both rising and falling edges. tJLT is defined as the long-term
jitter.
tCYCLE
tJP = tCYCLE,max – tCYCLE, min. over many cycles
CLK
CLKB
Figure 10. Period Jitter
tCYCLE,i
tJC = tCYLCE,i – tCYCLE,i+1 over many consecutive cycles
CLK
CLKB
tCYCLE, i+1
Figure 11. Cycle-to-cycle Jitter
tPW+,i
tDC,ERR = tPW+,i – tPW+,i+1 over many consecutive cycles
CLK
CLKB
tPW+,i+1
tCYCLE,i+1
tCYCLE, i+1
Cycle i
Cycle i+1
Figure 12. Cycle-to-cycle Duty Cycle Error
tJLT = tmax – tmin over many cycles
CLK
CLKB
tmin
tmax
Figure 13. Long-term Jitter
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