CY2213
Document #: 38-07263 Rev. *E
Page 2 of 10
CY2213 Two-Wire Serial Interface
Introduction
The CY2213 has a two-wire serial interface designed for data
transfer operations, and is used for programming the P and Q
values for frequency generation. Sclk is the serial clock line
controlled by the master device. Sdata is a serial bidirectional
data line. The CY2213 is a slave device and can either read or
write information on the dataline upon request from the master
device.
Figure 1 shows the basic bus connections between master
and slave device. The buses are shared by a number of
devices and are pulled high by a pull-up resistor.
Serial Interface Specifications
Figure 2 shows the basic transmission specification. To begin
and end a transmission, the master device generates a start
signal (S) and a stop signal (P). Start (S) is defined as
switching the Sdata from HIGH to LOW while the Sclk is at
HIGH. Similarly, stop (P) is defined as switching the Sdata from
LOW to HIGH while holding the Sclk HIGH. Between these two
signals, data on Sdata is synchronous with the clock on the Sclk.
Data is allowed to change only at LOW period of clock, and
must be stable at the HIGH period of clock. To acknowledge,
drive the Sdata LOW before the Sclk rising edge and hold it
LOW until the Sclk falling edge.
Serial Interface Format
Each slave carries an address. The data transfer is initiated by
a start signal (S). Each transfer segment is 1 byte in length.
The slave address and the read/write bit are first sent from the
master device after the start signal. The addressed slave
device must acknowledge (Ack) the master device. Depending
on the Read/Write bit, the master device will either write data
into (logic 0) or read data (logic 1) from the slave device. Each
time a byte of data is successfully transferred, the receiving
device must acknowledge. At the end of the transfer, the
master device will generate a stop signal (P).
Serial Interface Transfer Format
Figure 2 shows the serial interface transfer format used with
the CY2213. Two dummy bytes must be transferred before the
first data byte. The CY2213 has only three bytes of latches to
store information, and the third byte of data is reserved. Extra
data will be ignored.
Pin Description
Pin Name
Pin Number
Pin Description
VDDX
1
3.3V Power Supply for Crystal Driver
VSSX
2
Ground for Crystal Driver
XOUT
3
Reference Crystal Feedback
XIN
4
Reference Crystal Input
VDD
5
3.3 V Power Supply (all VDD pins must be tied directly on board)
OE
6
Output Enable, 0 = output disable, 1 = output enable (no internal pull-up)
VSS
7
Ground
SER CLK
8
Serial Interface Clock
SER DATA
9
Serial Interface Data
VDD
10
3.3V Power Supply (all VDD pins must be tied directly on board)
VSS
11
Ground
CLKB
12
LVPECL Output Clock (complement)
CLK
13
LVPECL Output Clock
VSS
14
Ground
VDD
15
3.3V Power Supply (all VDD pins must be tied directly on board)
S
16
PLL Multiplier Select Input, Pull-up Resistor Internal
Frequency Table
S
M (PLL Multiplier)
Example Input Crystal Frequency
CLK,CLKB
0
x16
25 MHz
400 MHz
31.25 MHz
500 MHz
1
x8
15.625 MHz
125 MHz
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