CY2213
Document #: 38-07263 Rev. *E
Page 4 of 10
PLL Frequency = Reference x P/Q = Output
Absolute Maximum Conditions
The following table reflects stress ratings only, and functional
operation at the maximums are not guaranteed.
Crystal Requirements
Requirements to use parallel mode fundamental xtal. External
capacitors are required in the crystal oscillator circuit. Please
refer to the application note entitled Crystal Oscillator Topics
for details.
DC Electrical Specifications
AC Electrical Specifications
Reference
PLL
Q
P
VCO
Φ
Output
Figure 4. PLL Block Diagram
Parameter
Description
Min.
Max.
Unit
VDD,ABS
Max. voltage on VDD, or VDDX with respect to ground
–0.5
4.0
V
VI, ABS
Max. voltage on any pin with respect to ground
–0.5
VDD+0.5
V
Parameter
Description
Min.
Max.
Unit
XF
Frequency
10
31.25
MHz
Parameter
Description
Min.
Max.
Unit
VDD
Supply voltage
3.00
3.60
V
TA
Ambient operating temperature
0
70
°C
VIL
Input signal low voltage at pin S
0.35
VDD
VIH
Input signal high voltage at pin S
0.65
VDD
RPUP
Internal pull-up resistance
10
100
k
Ω
tPU
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
0.05
500
ms
Parameter
Description
Min.
Max.
Unit
fIN
Input frequency with driven reference
1
133
MHz
fXTAL,IN
Input frequency with crystal input
10
31.25
MHz
CIN,CMOS
Input capacitance at S pin[1]
10
pF
3.3V DC Device Characteristics (Driving load, Figure 5)
Parameter
Description
Min.
Typ.
Max.
Unit
VOH
Output high voltage, referenced to VDD
–1.02
–0.95
–0.88
V
VOL
Output low voltage, referenced to VDD
–1.81
–1.70
–1.62
V
3.3V DC Device Characteristics (Driving load, Figure 6)
Parameter
Description
Min.
Typ.
Max.
Unit
VOH
Output high voltage
1.1
1.2
1.3
V
VOL
Output low voltage
0
0
0
V
Note:
1.
Capacitance measured at freq. = 1 MHz, DC Bias = 0.9V, and VAC < 100 mV.
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