AD9212-65EBZ datasheet(33/57 Pages) AD

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AD9212

Data Sheet

Rev. E | Page 32 of 56

NUMBER OF SDIO PINS CONNECTED TOGETHER

1.715

1.720

1.725

1.730

1.735

1.740

1.745

1.750

1.755

1.760

1.765

1.770

1.775

1.780

1.785

1.790

1.795

1.800

030

100

Figure 67. SDIO Pin Loading

DON’T CARE

SDIO

SCLK

CSB

tDH

tHI

tCLK

tLO

tDS

R/W

A12

A11

A10

Figure 68. Serial Timing Details

Table 15. Serial Timing Definitions

Parameter

Timing (Minimum, ns)

Description

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the clock

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHI

Minimum period that SCLK should be in a logic high state

tLO

Minimum period that SCLK should be in a logic low state

tEN_SDIO

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK

falling edge (not shown in Figure 68)

tDIS_SDIO

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK

rising edge (not shown in Figure 68)

AD9212-65EBZ Datasheet(PDF) 33 Page - Analog Devices

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