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AD9460

Rev. 0 | Page 10 of 32

D4+

D3+

D2+

DNC

D0+ (LSB)

D1+

DRGND

DCO+

DCO–

DNC

DRVDD

DRGND

DNC

PIN 1

DNC = DO NOT CONNECT

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

DNC

OUTPUT MODE

DFS

SENSE

AVDD1

LVDS_BIAS

DCS MODE

VREF

AGND

REFT

AVDD2

AVDD1

AGND

VIN+

VIN–

AGND

AVDD2

REFB

AD9460

CMOS MODE

TOP VIEW

(Not to Scale)

Figure 5. 100-Lead TQFP_EP Pin Configuration in CMOS Mode

Table 8. Pin Function Descriptions—100-Lead TQFP_EP in CMOS Mode

Pin No.

Mnemonic

Description

DCS MODE

Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible.

DCS = low (AGND) to enable DCS (recommended).

DCS = high (AVDD1) to disable DCS.

2, 49 to 62, 65 to 66, 69

DNC

Do Not Connect. These pins should float.

OUTPUT MODE

CMOS-Compatible Output Logic Mode Control Pin.

OUTPUT MODE = 0 for CMOS mode.

OUTPUT MODE = 1 (AVDD1) for LVDS outputs.

DFS

Data Format Select Pin. CMOS control pin that determines the format of the output data.

DFS = high (AVDD1) for twos complement.

DFS = low (ground) for offset binary format.

LVDS_BIAS

Set Pin for LVDS Output Current. Place a 3.7 kΩ resistor terminated to DRGND.

6, 18 to 20, 32 to 34, 36,

38, 43 to 45, 92 to 97

AVDD1

3.3 V (±5%) Analog Supply.

SENSE

Reference Mode Selection. Connect to AGND for internal 1.7 V reference (3.4 V p-p analog

input range); connect to AVDD1 for external reference.

VREF

1.7 V Reference I/O. The function is dependent on the SENSE pin and external programming

resistors. Decouple to ground with 0.1 μF and 10 μF capacitors.

9, 21, 24, 39, 42, 46, 91, 98,

99, Exposed Heat Sink

AGND

Analog Ground. The exposed heat sink on the bottom of the package must be connected

to AGND.

REFT

Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB (Pin

11) with 0.1 μF and 10 μF capacitors.

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