AD9461 datasheet(19/29 Pages) AD

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AD9461

Rev. 0 | Page 18 of 28

Table 9. Reference Configuration Summary

Selected Mode

SENSE Voltage

Resulting VREF (V)

Resulting Differential Span (V p-p)

External Reference

AVDD

N/A

2 × external reference

Programmable Reference

0.2 V to VREF

⎟

⎠

⎞

⎜

⎝

⎛ +

0.5

, (See Figure 30)

2 × VREF

Programmable Reference

(Set for 2 V p-p)

0.2 V to VREF

⎟

⎠

⎞

⎜

⎝

⎛ +

0.5

, R1 = R2 = 1 kΩ

2.0

Internal Fixed Reference

AGND to 0.2 V

1.7

3.4

External Reference Operation

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7 kΩ load. The internal buffer continues to generate the positive

and negative full-scale references, REFT and REFB, for the

ADC core. The input span is always twice the value of the

reference voltage; therefore, the external reference must be

limited to a maximum of 2.0 V. See Figure 24 for gain variation vs.

temperature.

Analog Inputs

As with most new high speed, high dynamic range ADCs, the

analog input to the AD9461 is differential. Differential inputs

improve on-chip performance because signals are processed

through attenuation and gain stages. Most of the improvement

is a result of differential analog stages having high rejection of

even-order harmonics. There are also benefits at the PCB level.

First, differential inputs have high common-mode rejection of

stray signals, such as ground and power noise. Second, they

provide good rejection of common-mode signals, such as local

oscillator feedthrough. The specified noise and distortion of the

AD9461 cannot be realized with a single-ended analog input;

therefore, such configurations are discouraged. Contact sales for

recommendations of other 16-bit ADCs that support single-

ended analog input configurations.

With the 1.7 V reference, which is the nominal value (see the

Internal Reference Trim section), the differential input range of

the AD9461 analog input is nominally 3.4 V p-p or 1.7 V p-p on

each input (VIN+ or VIN−).

3.5V

VIN+

VIN–

1.7V p-p

DIGITAL OUT = ALL 1s

DIGITAL OUT = ALL 0s

Figure 31. Differential Analog Input Range for VREF = 1.7 V

The AD9461 analog input voltage range is offset from ground

by 3.5 V. Each analog input connects through a 1 kΩ resistor to

the 3.5 V bias voltage and to the input of a differential buffer. The

internal bias network on the input properly biases the buffer for

maximum linearity and range (see the Equivalent Circuits section).

Therefore, the analog source driving the AD9461 should be ac-

coupled to the input pins. The recommended method for driving

the analog input of the AD9461 is to use an RF transformer to

convert single-ended signals to differential (see Figure 32). Series

resistors between the output of the transformer and the AD9461

analog inputs help isolate the analog input source from switching

transients caused by the internal sample-and-hold circuit. The

series resistors, along with the 1 kΩ resisters connected to the

internal 3.5 V bias, must be considered in impedance matching

the transformer input. For example, if RT is set to 51 Ω, RS is set

to 33 Ω and there is a 1:1 impedance ratio transformer, the input

matches a 50 Ω source with a full-scale drive of 16.0 dBm. The

50 Ω impedance matching can also be incorporated on the

secondary side of the transformer, as shown in the evaluation

board schematic (see Figure 35).

0.1µF

AD9461

VIN+

VIN–

ADT1–1WT

ANALOG

INPUT

SIGNAL

Figure 32. Transformer-Coupled Analog Input Circuit

CLOCK INPUT CONSIDERATIONS

Any high speed ADC is extremely sensitive to the quality of the

sampling clock provided by the user. A track-and-hold circuit is

essentially a mixer, and any noise, distortion, or timing jitter on

the clock combines with the desired signal at the analog-to-

digital output. For that reason, considerable care was taken in

the design of the clock inputs of the AD9461, and the user is

advised to give careful thought to the clock source.

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals and, as a result, can be sensitive

to the clock duty cycle. Commonly a 5% tolerance is required on

the clock duty cycle to maintain dynamic performance charac-

teristics. The AD9461 contains a clock duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal ~50% duty cycle. Noise and distortion per-

formance are nearly flat for a 30% to 70% duty cycle with the DCS

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