ADC12DL040 datasheet(3/26 Pages) NSC

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Pin Descriptions and Equivalent Circuits

Pin No.

Symbol

Equivalent Circuit

Description

ANALOG I/O

INA+

INB+

Differential analog input pins. With a 1.0V reference voltage the

differential full-scale input signal level is 2.0 V

P-P with each

input pin voltage centered on a common mode voltage, V

CM.

The negative input pins may be connected to V

CM for

single-ended operation, but a differential input signal is

required for best performance.

INA−

INB−

REF

This pin is the reference select pin and the external reference

input.

If (V

A - 0.3V) < VREF < VA, the internal 1.0V reference is

selected.

If AGND < V

REF < (AGND + 0.3V), the internal 0.5V reference

is selected.

If a voltage in the range of 0.8V to 1.2V is applied to this pin,

that voltage is used as the reference. V

REF should be

bypassed to AGND with a 0.1 µF capacitor when an external

reference is used.

DF/DCS

This is a four-state pin.

DF/DCS = V

A, output data format is offset binary with duty

cycle stabilization applied to the input clock

DF/DCS = AGND, output data format is 2’s complement, with

duty cycle stabilization applied to the input clock.

DF/DCS = V

RMAorVRMB , output data is 2’s complement

without duty cycle stabilization applied to the input clock

DF/DCS = "float", output data is offset binary without duty cycle

stabilization applied to the input clock.

RPA

RPB

These pins are high impedance reference bypass pins. All

these pins should each be bypassed to ground with a 0.1 µF

capacitor. A 10 µF capacitor should be placed between the

RPA and VRNA pins and between the VRPB and VRNB pins.

RMA and VRMB may be loaded to 1mA for use as a

temperature stable 1.5V reference. The remaining pins should

not be loaded.

RMA

RMB

RNA

RNB

DIGITAL I/O

CLK

Digital clock input. The range of frequencies for this input is as

specified in the electrical tables with guaranteed performance

at 40 MHz. The input is sampled on the rising edge.

OEA

OEB

OEA and OEB are the output enable pins that, when low, holds

their respective data output pins in the active state. When

either of these pins is high, the corresponding outputs are in a

high impedance state.

ADC12DL040 Datasheet(PDF) 3 Page - National Semiconductor (TI)

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