ADC12DL040 datasheet(4/26 Pages) NSC

4 / 26 page

Pin Descriptions and Equivalent Circuits (Continued)

Pin No.

Symbol

Equivalent Circuit

Description

PD is the Power Down input pin. When high, this input puts the

converter into the power down mode. When this pin is low, the

converter is in the active mode.

MULTIPLEX

When low, "A" and "B" data is present on it’s respective data

output lines (Parallel Mode).

When high, both "A" and "B" channel data is present on the

"DA0:DA11" digital outputs (Multiplex Mode). The DB0/ABb pin

is used to synchronize the data.

24–29

34–39

DA0–DA11

Digital data output pins that make up the 12-bit conversion

results of their respective converters. DA0 and DB0 are the

LSBs, while DA11 and DB11 are the MSBs of the output word.

Output levels are TTL/CMOS compatible. Optimum loading is

< 10pF.

43–47

52–57

DB1–DB11

DB0/ABb

When MULTIPLEX is low, this is DB0.

When MULTIPLEX is high this is the ABb signal, which is used

to synchronize the multiplexed data. ABb changes

synchronously with the Multiplexed "A" and "B" channels. ABb

is "high" when "A" channel data is valid and is "low" when "B"

channel data is valid.

ANALOG POWER

9, 18, 19,

62, 63

Positive analog supply pins. These pins should be connected

to a quiet +3.0V source and bypassed to AGND with 0.1 µF

capacitors located within 1 cm of these power pins, and with a

10 µF capacitor.

3, 8, 10, 17,

20, 61, 64

AGND

The ground return for the analog supply.

DIGITAL POWER

33, 48

Positive digital supply pin. This pin should be connected to the

same quiet +3.0V source as is V

A and be bypassed to DGND

with a 0.1 µF capacitor located within 1 cm of the power pin

and with a 10 µF capacitor.

32, 49

DGND

The ground return for the digital supply.

30, 51

Positive driver supply pin for the ADC12DL040’s output drivers.

This pin should be connected to a voltage source of +2.4V to

D and be bypassed to DR GND with a 0.1 µF capacitor. If the

supply for this pin is different from the supply used for V

A and

D, it should also be bypassed with a 10 µF capacitor. VDR

should never exceed the voltage on V

D. All 0.1 µF bypass

capacitors should be located within 1 cm of the supply pin.

23, 31, 40,

50, 58

DR GND

The ground return for the digital supply for the ADC12DL040’s

output drivers. These pins should be connected to the system

digital ground, but not be connected in close proximity to the

ADC12DL040’s DGND or AGND pins. See Section 5 (Layout

and Grounding) for more details.

ADC12DL040 Datasheet(PDF) 4 Page - National Semiconductor (TI)

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