ADC12DL040 datasheet(8/26 Pages) NSC

8 / 26 page

AC Electrical Characteristics (Continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V

A =VD = +3.0V, VDR =

+2.5V, PD = 0V, External V

REF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr =tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On,

parallel output mode. Boldface limits apply for T

J =TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 12)

Symbol

Parameter

Conditions

Typical

(Note 10)

Limits

(Note 10)

Units

(Limits)

CONV

Conversion Latency

Multiplex mode, Channel A

7.5

Clock

Cycles

CONV

Conversion Latency

Multiplex mode, Channel B

Clock

Cycles

Data Output Delay after Clock

Edge

Multiplex mode

6.0

3.5

ns (min)

ns (max)

SKEW

ABb to Data Skew

±0.5

ns (max)

Aperture Delay

Aperture Jitter

1.2

ps rms

DIS

Data outputs into Hi-Z Mode

Data Outputs Active after Hi-Z

Mode

Power Down Mode Exit Cycle

1.0 µF on pins 4, 14; 0.1 µF on pins

5,6,12,13; 10 µF between pins 5, 6

and between pins 12, 13

1µs

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to 25 mA. The

50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the

junction-to-ambient thermal resistance (

θJA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX=(TJmax - TA )/θJA. In the 64-pin

TQFP,

θJA is 50˚C/W, so PDMAX=2Watts at 25˚C and 800 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of this

device under normal operation will typically be about 250 mW (210 typical power consumption + 40 mW TTL output loading). The values for maximum power

dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power

supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k

Ω resistor. Machine model is 220 pF discharged through 0Ω.

Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.

Note 7: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per

(Note 3). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale

input voltage must be

≤+3.4V to ensure accurate conversions.

20100207

Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

Note 9: With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.

Note 10: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality

Level).

Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative

full-scale.

Note 12: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge.

Note 13: Optimum performance will be obtained by keeping the reference input in the 0.8V to 1.2V range. The LM4051CIM3-ADJ (SOT-23 package) is

recommended for external reference applications.

Note 14: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,

VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 xf0 +C1 xf1 +....C11 xf11) where VDR is the output driver power supply

voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling.

Note 15: Excludes IDR. See note 14.

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