AD9238 datasheet(19/49 Pages) AD

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AD9238

Rev. C | Page 18 of 48

A single channel can be powered down for moderate power

savings. The powered-down channel shuts down internal

circuits, but both the reference buffers and shared reference

remain powered on. Because the buffer and voltage reference

remain powered on, the wake-up time is reduced to several

clock cycles.

POWER DISSIPATION AND STANDBY MODE

The power dissipated by the AD9238 is proportional to its

sampling rates. The digital (DRVDD) power dissipation is

determined primarily by the strength of the digital drivers and

the load on each output bit. The digital drive current can be

calculated by

DIGITAL OUTPUTS

IDRVDD = VDRVDD × CLOAD × fCLOCK × N

The AD9238 output drivers can be configured to interface with

2.5 V or 3.3 V logic families by matching DRVDD to the digital

supply of the interfaced logic. The output drivers are sized to

provide sufficient output current to drive a wide variety of logic

families. However, large drive currents tend to cause current

glitches on the supplies that may affect converter performance.

Applications requiring the ADC to drive large capacitive loads

or large fanouts may require external buffers or latches.

where N is the number of bits changing, and CLOAD is the average

load on the digital pins that changed.

The analog circuitry is optimally biased so that each speed

grade provides excellent performance while affording reduced

power consumption. Each speed grade dissipates a baseline

power at low sample rates that increases with clock frequency.

Either channel of the AD9238 can be placed into standby mode

independently by asserting the PDWN_A or PDWN_B pins.

The data format can be selected for either offset binary or twos

complement. See the Data Format section for more information.

It is recommended that the input clock(s) and analog input(s)

remain static during either independent or total standby, which

results in a typical power consumption of 1 mW for the ADC.

Note that if DCS is enabled, it is mandatory to disable the clock

of an independently powered-down channel. Otherwise,

significant distortion results on the active channel. If the clock

inputs remain active while in total standby mode, typical power

dissipation of 12 mW results.

TIMING

The AD9238 provides latched data outputs with a pipeline delay

of seven clock cycles. Data outputs are available one propa-

gation delay (tPD) after the rising edge of the clock signal. Refer

to Figure 2 for a detailed timing diagram.

The internal duty cycle stabilizer can be enabled on the AD9238

using the DCS pin. This provides a stable 50% duty cycle to

internal circuits.

The minimum standby power is achieved when both channels

are placed into full power-down mode (PDWN_A = PDWN_B =

HI). Under this condition, the internal references are powered

down. When either or both of the channel paths are enabled after a

power-down, the wake-up time is directly related to the recharging

of the REFT and REFB decoupling capacitors and to the duration

of the power-down. Typically, it takes approximately 5 ms to

restore full operation with fully discharged 0.1 μF and 10 μF

decoupling capacitors on REFT and REFB.

The length of the output data lines and loads placed on them

should be minimized to reduce transients within the AD9238.

These transients can detract from the converter’s dynamic

performance. The lowest typical conversion rate of the AD9238

is 1 MSPS. At clock rates below 1 MSPS, dynamic performance

may degrade.

B–8

A–7

B–7

A–6

B–6

A–5

B–5

A–4

B–4

A–3

B–3

A–2

B–2

A–1

B–1

A–1

B–1

ANALOG INPUT

ADC A

ANALOG INPUT

ADC B

CLK_A = CLK_B =

MUX_SELECT

D0_A TO

D11_A

tPD

Figure 34. Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT

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