ADAU1361BCPZ-R7 datasheet(28/81 Pages) AD

28 / 81 page

ADAU1361

Rev. C | Page 27 of 80

PLL

The PLL uses the MCLK as a reference to generate the core

clock. PLL settings are set in Register R1 (PLL control register,

Address 0x4002). Depending on the MCLK frequency, the PLL

must be set for either integer or fractional mode. The PLL can

accept input frequencies in the range of 8 MHz to 27 MHz.

All six bytes in the PLL control register must be written with a

single continuous write to the control port.

MCLK

÷ X

× (R + N/M)

TO PLL

CLOCK DIVIDER

Figure 30. PLL Block Diagram

Integer Mode

Integer mode is used when the MCLK is an integer (R) multiple

of the PLL output (1024 × fS).

For example, if MCLK = 12.288 MHz and fS = 48 kHz, then

PLL required output = 1024 × 48 kHz = 49.152 MHz

R = 49.152 MHz/12.288 MHz = 4

In integer mode, the values set for N and M are ignored.

Fractional Mode

Fractional mode is used when the MCLK is a fractional

(R + (N/M)) multiple of the PLL output.

For example, if MCLK = 12 MHz and fS = 48 kHz, then

PLL required output = 1024 × 48 kHz = 49.152 MHz

R + (N/M) = 49.152 MHz/12 MHz = 4 + (12/125)

Common fractional PLL parameter settings for 44.1 kHz and

48 kHz sampling rates can be found in Table 16 and Table 17.

The PLL outputs a clock in the range of 41 MHz to 54 MHz,

which should be taken into account when calculating PLL

values and MCLK frequencies.

Table 15. PLL Control Register (Register R1, Address 0x4002)

Bits

Bit Name

Description

[47:32]

M[15:0]

Denominator of the fractional PLL: 16-bit binary number

0x00FD: M = 253 (default)

[31:16]

N[15:0]

Numerator of the fractional PLL: 16-bit binary number

0x000C: N = 12 (default)

[14:11]

R[3:0]

Integer part of PLL: four bits, only values 2 to 8 are valid

0010: R = 2 (default)

0011: R = 3

0100: R = 4

0101: R = 5

0110: R = 6

0111: R = 7

1000: R = 8

[10:9]

X[1:0]

PLL input clock divider

00: X = 1 (default)

01: X = 2

10: X = 3

11: X = 4

Type

PLL operation mode

0: Integer (default)

1: Fractional

Lock

PLL lock (read-only bit)

0: PLL unlocked (default)

1: PLL locked

PLLEN

PLL enable

0: PLL disabled (default)

1: PLL enabled

ADAU1361BCPZ-R7 Datasheet(PDF) 28 Page - Analog Devices

ADAU1361BCPZ-R7 Datasheet(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Datasheet Download

Link URL