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SCANSTA111 Datasheet(PDF) 14 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # SCANSTA111
Description  Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port
PDF  29 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

SCANSTA111 Datasheet(HTML) 14 Page - National Semiconductor (TI)

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Level 2 Protocol (Continued)
TABLE 5. Level 2 Protocol and Op-Codes (Continued)
Instructions
Hex Op-Code
Binary Op-Code
Data Register
DGPIO
4
B4
1011 0100
Dedicated GPIO Register
4
DGPIO
5
B5
1011 0101
Dedicated GPIO Register
5
DGPIO
6
B6
1011 0110
DedicateD GPIO Register
6
DGPIO
7
B7
1011 0111
Dedicated GPIO Register
7
SGPIO
0
B8
1011 1000
Shared GPIO Register
0
SGPIO
1
B9
1011 1001
Shared GPIO Register
1
SGPIO
2
BA
1011 1010
Shared GPIO Register
2
SGPIO
3
BB
1011 1011
Shared GPIO Register
3
SGPIO
4
BC
1011 1100
Shared GPIO Register
4
SGPIO
5
BD
1011 1101
Shared GPIO Register
5
SGPIO
6
BE
1011 1110
Shared GPIO Register
6
SGPIO
7
BF
1011 1111
Shared GPIO Register
7
Other Undefined
TBD
TBD
Device Identification Register
Note 8: All other instructions act on selected STA111s only.
Note 9: Commands added to HDL version of STA111.
LEVEL 2 INSTRUCTON DESCRIPTIONS:
BYPASS: The BYPASS instruction selects the bypass reg-
ister for insertion into the active scan chain when the
’STA111 is selected.
EXTEST: The EXTEST instruction selects the boundary-
scan register for insertion into the active scan chain. The
boundary-scan register consists of seven sample only shift
cells connected to the S
(0-6) and OE inputs. On the ’STA111,
the EXTEST instruction performs the same function as the
SAMPLE/PRELOAD instruction, since there aren’t any scan-
nable outputs on the device.
SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction
selects the boundary-scan register for insertion into the ac-
tive scan chain. The boundary-scan register consists of
seven sample only shift cells connected to the S
(0-6) and OE
inputs.
IDCODE: The IDCODE instruction selects the device identi-
fication register for insertion into the active scan chain. When
IDCODE is the current active instruction the device identifi-
cation 0FC0F01F Hex is captured upon exiting the
Capture-DR state.
UNPARK: This instruction unparks the Local Scan Port Net-
work and inserts it into the active scan chain as configured
by Mode Register
0 (and Mode Register1 in the HDL) (see
Table 7). Unparked LSPs are sequenced synchronously with
the ’STA111’s TAP controller. When a LSP has been parked
in the Test-Logic-Reset or Run-Test/Idle state, it will not
become unparked until the ’STA111’s TAP Controller enters
the Run-Test/Idle state following the UNPARK instruction. An
LSP which has been parked in Test-Logic-Reset will be
parked in Run-Test/Idle upon update of an UNPARK instruc-
tion. If an LSP has been parked in one of the stable pause
states (Pause-DR or Pause-IR), it will not become unparked
until the ’STA111’s TAP Controller enters the respective
pause state. (See Figure 9, Figure 10, Figure 11, and Figure
12).
PARKTLR: This instruction causes all unparked LSPs to be
parked in the Test-Logic-Reset TAP controller state and
removes the LSP network from the active scan chain. The
LSP controllers keep the LSPs parked in the Test-Logic-
Reset state by forcing their respective TMS
n output with a
constant logic 1 while the LSP controller is in the Parked-
TLR state (see Figure 4).
PARKRTI: This instruction causes all unparked LSPs to be
parked in the Run-Test/Idle state. The update of the
PARKRTI instruction MUST immediately be followed by a
TMS
B=0 (to enter the RTI state) in order to assure stability.
When a LSP
n is active (unparked), its TMSn signals follow
TMS
B and the LSPn controller state transitions are synchro-
nized with the TAP Controller state transitions of the
’STA111. When the instruction register is updated with the
PARKRTI instruction, TMS
n will be forced to a constant logic
0, causing the unparked local TAP Controllers to be parked
in the Run-Test/Idle state. When an LSP
n is parked, it is
removed from the active scan chain.
PARKPAUSE: The PARKPAUSE instruction has dual func-
tionality. It can be used to park unparked LSPs or to unpark
parked LSPs. The instruction places all unparked LSPs in
one of the TAP Controller pause states. A local port does not
become parked until the ’STA111’s TAP Controller is se-
quenced through Exit1-DR/IR into the Update-DR/IR state.
When the ’STA111 TAP Controller is in the Exit1-DR or
Exit1-IR state and TMSB is high, the LSP controller forces a
constant logic 0 onto TMSL thereby parking the port in the
Pause-DR or Pause-IR state respectively (see Figure 4).
Another instruction can then be loaded to reconfigure the
local ports or to deselect the ’STA111 (i.e., MODESEL, GO-
TOWAIT, etc.).
If the PARKPAUSE instruction is given to a whose LSPs are
parked in Pause-IR or Pause-DR, the parked LSPs will
become unparked when the ’STA111’s TAP controller is se-
quenced into the respective Pause state.
The PARKPAUSE instruction was implemented with this
dual functionality to enable backplane testing (interconnect
testing between boards) with simultaneous Updates and
Captures.
Simultaneous Update and Capture of several boards can be
performed by parking LSPs of the different boards in the
Pause-DR TAP controller state, after shifting the data to be
updated into the boundary registers of the components on
each board. The broadcast address is used to select all
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