HD6473048 datasheet(6/867 Pages) HITACHI

6 / 867 page

6.3.6

Interconnections with Memory (Example) ..................................................... 139

6.3.7

Bus Arbiter Operation..................................................................................... 141

6.4

Usage Notes .................................................................................................................... 144

6.4.1

Connection to Dynamic RAM and Pseudo-Static RAM ................................ 144

6.4.2

6.4.3

BREQ Input Timing........................................................................................ 144

6.4.4

Transition to Software Standby Mode ............................................................ 146

Section 7

Refresh Controller .................................................................................... 147

7.1

Overview......................................................................................................................... 147

7.1.1

Features........................................................................................................... 147

7.1.2

Block Diagram................................................................................................ 148

7.1.3

Input/Output Pins............................................................................................ 149

7.1.4

7.2

Register Descriptions...................................................................................................... 150

7.2.1

Refresh Control Register (RFSHCR) ............................................................. 150

7.2.2

Refresh Timer Control/Status Register (RTMCSR) ....................................... 153

7.2.3

Refresh Timer Counter (RTCNT)................................................................... 155

7.2.4

Refresh Time Constant Register (RTCOR) .................................................... 155

7.3

Operation ........................................................................................................................ 156

7.3.1

Overview......................................................................................................... 156

7.3.2

DRAM Refresh Control.................................................................................. 157

7.3.3

Pseudo-Static RAM Refresh Control.............................................................. 172

7.3.4

Interval Timing ............................................................................................... 177

7.4

Interrupt Source .............................................................................................................. 183

7.5

Usage Notes .................................................................................................................... 183

Section 8

DMA Controller ........................................................................................ 185

8.1

Overview......................................................................................................................... 185

8.1.1

Features........................................................................................................... 185

8.1.2

Block Diagram................................................................................................ 186

8.1.3

Functional Overview....................................................................................... 187

8.1.4

Input/Output Pins............................................................................................ 188

8.1.5

8.2

8.2.1

Memory Address Registers (MAR)................................................................ 190

8.2.2

I/O Address Registers (IOAR)........................................................................ 191

8.2.3

Execute Transfer Count Registers (ETCR)..................................................... 191

8.2.4

Data Transfer Control Registers (DTCR) ....................................................... 193

8.3

8.3.1

Memory Address Registers (MAR)................................................................ 196

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