| Electronic Components Datasheet Search |
|
HD6473048 Datasheet(PDF) 18 Page - Hitachi Semiconductor |
|
|
|||||||||||||||||||||||||||||
HD6473048 Datasheet(HTML) 18 Page - Hitachi Semiconductor |
|
18 / 867 page ![]() Table 1-1 Features (cont) Feature Description Refresh DRAM refresh controller • Directly connectable to 16-bit-wide DRAM • CAS-before-RAS refresh • Self-refresh mode selectable Pseudo-static RAM refresh • Self-refresh mode selectable Usable as an interval timer DMA controller Short address mode (DMAC) • Maximum four channels available • Selection of I/O mode, idle mode, or repeat mode • Can be activated by compare match/input capture A interrupts from ITU channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, or external requests Full address mode • Maximum two channels available • Selection of normal mode or block transfer mode • Can be activated by compare match/input capture A interrupts from ITU channels 0 to 3, external requests, or auto-request 16-bit integrated • Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10 timer unit (ITU) pulse inputs • 16-bit timer counter (channels 0 to 4) • Two multiplexed output compare/input capture pins (channels 0 to 4) • Operation can be synchronized (channels 0 to 4) • PWM mode available (channels 0 to 4) • Phase counting mode available (channel 2) • Buffering available (channels 3 and 4) • Reset-synchronized PWM mode available (channels 3 and 4) • Complementary PWM mode available (channels 3 and 4) • DMAC can be activated by compare match/input capture A interrupts (channels 0 to 3) Programmable • Maximum 16-bit pulse output, using ITU as time base timing pattern • Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups) controller (TPC) • Non-overlap mode available • Output data can be transferred by DMAC Watchdog • Reset signal can be generated by overflow timer (WDT), • Reset signal can be output externally 1 channel • Usable as an interval timer Serial • Selection of asynchronous or synchronous mode communication • Full duplex: can transmit and receive simultaneously interface (SCI), • On-chip baud-rate generator 2 channels • Smart card interface functions added (SCI0 only) 3 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |