FDMF8811 datasheet(13/19 Pages) ONSEMI

13 / 19 page

FDMF8811

www.onsemi.com

refers to VDD power supply at primary side and

“VDD_SS” refers to VDD power supply at secondary

side.

VDD_PS

VDD_SS

CTRL

PWM

VOUT

PWM forbidden zone

> 5ms

Figure 22 VDD power supply timing sequence during

start up

A correct timing sequence is also required when

powering down a DC-DC conversion system to avoid

overstress or even damage of the components in the

system. It is highly recommended to configure the power

system to have more than 5 milliseconds time margin

between the event that the controller pulls down PWM

signals and the event the driver power supplies are turn

off. The PWM forbidden region illustrated in Figure 23

suggests no PWM signal 5 milliseconds before VDD

power supplies starts to lose regulation.

VDD_PS

VDD_SS

CTRL

PWM

VOUT

PWM forbidden zone

> 5ms

Figure 23 VDD power supply timing sequence during

power down

PCB Layout Guideline

There are several loops with the high frequency pulsing

current, including the input voltage loop and two gate

driver loops. It is critical to keep the loop impedance as

low as possible. All of the high current paths, such as

VIN, SW and PGND, should be short and wide for low

parasitic inductance and resistance. This helps achieve a

more stable and evenly distributed current flow, along

with enhanced heat radiation and system performance.

Input ceramic bypass capacitors must be close to the

VIN and PGND pins. This reduces the high-current

power loop inductance and the input current ripple

induced by the power MOSFET switching operation.

The SW copper trace serves two purposes. In addition to

being the high-frequency current path from the

FDMF8811 package to the output inductor, it serves as a

heat sink for the low-side MOSFET in the FDMF8811

package. The trace should be short and wide enough to

present a low-impedance path for the high-frequency,

high-current flow between the FDMF8811 and inductor.

The short and wide trace minimizes electrical losses as

well as the FDMF8811 temperature rises.

Note that the SW node is a high-voltage and high-

frequency switching node with high noise potential. Care

should be taken to minimize coupling to adjacent traces.

Since this copper trace acts as a heat sink for the low-

side MOSFET, balance using the largest area possible to

improve FDMF8811 cooling while maintaining

acceptable noise emission.

An output inductor should be located close to the

FDMF8811 to minimize the power loss due to the SW

copper trace. Care should also be taken so the inductor

dissipation does not heat the FDMF8811.

PowerTrench® MOSFETs are used in the output stage

and are effective at minimizing ringing due to fast

switching. In most cases, no R&C snubber on SW node

is required. If a snubber is used, it should be placed close

to the SW and PGND pins.

The board layout should include a placeholder for small-

value series boot resistor in series to the BOOT

capacitor. The boot-loop size, including series RBOOT

and CBOOT, should be as small as possible.

The boot resistor may be required when there is large

ringing at SW pin, and it is effective to control the high-

side MOSFET turn-on slew rate and SW voltage

overshoot. RBOOT can improve noise operating margin

if there is large switching noise due to ground bounce or

high positive and negative SW ringing. Inserting a boot

resistance lowers the FDMF8811 module efficiency.

Efficiency versus switching noise trade-offs must be

considered.

The VIN and PGND pins handle large current transients

with frequency components greater than 100MHz. If

possible, these pins should be connected directly to the

VIN and board GND planes. The use of thermal relief

traces in series with these pins is not recommended since

this adds extra parasitic inductance to the power path.

This added inductance in series with either the VIN or

PGND pin degrades system noise immunity by

increasing positive and negative SW ringing.

PGND pad and pins should be connected to the GND

copper plane with multiple vias for stable grounding.

Poor grounding can create a noise transient offset

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