AD6649EBZ datasheet(28/41 Pages) AD

28 / 41 page

Data Sheet

AD6649

Rev. C | Page 27 of 40

DC CORRECTION

Because the dc offset of the ADC may be significantly larger

than the signal being measured, a dc correction circuit is included

to null the dc offset before measuring the power. The dc correction

circuit can also be switched into the main signal path, but this

may not be appropriate if the ADC is digitizing a time-varying

signal with significant dc content, such as GSM.

DC Correction Bandwidth

The dc correction circuit is a high-pass filter with a program-

mable bandwidth (ranging between 0.29 Hz and 2.387 kHz at

245.76 MSPS). The bandwidth is controlled by writing the 4-bit

dc correction bandwidth select register, located at Register 0x40,

Bits[5:2]. The following equation can be used to compute the

bandwidth value for the dc correction circuit:

CLK

Corr

where:

k is the 4-bit value programmed in Bits[5:2] of Register 0x40

(values between 0 and 13 are valid for k; programming 14 or 15

provides the same result as programming 13).

fCLK is the AD6649 ADC sample rate in hertz.

DC Correction Readback

The current dc correction value can be read back in Register 0x41

and Register 0x42 for each channel. The dc correction value is a

16-bit value that can span the entire input range of the ADC.

DC Correction Freeze

Setting Bit 6 of Register 0x40 freezes the DC correction at its

current state and continues to use the last updated value as the

dc correction value. Clearing this bit restarts dc correction and

adds the currently calculated value to the data.

DC Correction Enable Bits

Setting Bit 1 of Register 0x40 enables dc correction for use in

the output data signal path.

AD6649EBZ Datasheet(PDF) 28 Page - Analog Devices