AD9864BCPZ datasheet(27/48 Pages) AD

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AD9864

Data Sheet

Rev. A | Page 26 of 47

FREF

84kΩ

~VDDL/2

BUFFER

500Ω

TO MIXER

LO PORT

1.75V

BIAS

LOP

LON

NOTES

1. ESD DIODE STRUCTURES OMITTED FOR CLARITY.

2. FREF STBY SWITCHES SHOWN WITH LO SYNTHESIZER ON.

Figure 40. Equivalent Input of LO and REF Buffers

Figure 40 shows the equivalent input structures of the LO and

REF buffers of the synthesizers (excluding the ESD structures).

The LO input is fed to the buffer of the LO synthesizer as well as

the LO port of the AD9864 mixer. Both inputs are self biasing and

thus tolerate ac-coupled inputs. The LO input can be driven with

a single-ended or differential signal. Single-ended, dc-coupled

inputs ensure sufficient signal swing above and below the

common-mode bias of the LO and REF buffers (that is, 1.75 V

and VDDL/2). Note that the fREF input is slew rate dependent

and must be driven with input signals exceeding 7.5 V/µs to

ensure proper synthesizer operation. If this condition cannot be

met, an external logic gate can be inserted prior to the fREF input

to square up the signal, thus allowing an fREF input frequency

approaching dc.

Fast Acquire Mode

The fast acquire circuit attempts to boost the output current when

the phase difference between the divided-down LO (that is, fLO)

and the divided-down reference frequency (that is, fREF) exceeds

the threshold determined by the LOFA register. The LOFA

period (T) of this divided-down clock. This period defines the

time interval used in the fast acquire algorithm to control the

charge pump current.

Assume that the nominal charge pump current is at its lowest

setting (LOI = 0), and denote this minimum current by I0.

When the output pulse from the phase comparator exceeds T,

the output current for the next pulse is 2I0. When the pulse is

wider than 2T, the output current for the next pulse is 3I0, and

so forth, up to eight times the minimum output current. If the

nominal charge pump current is more than the minimum value

(LOI > 0), the preceding rule is only applied if it results in an

increase in the instantaneous charge pump current. If the

charge pump current is set to its lowest value (LOI = 0) and the

fast acquire circuit is enabled, the instantaneous charge pump

current never falls below 2I0when the pulse width is less than T.

Thus, the charge pump current when fast acquire is enabled is

given by

IPUMP-FA = I0 × [1 = Max(1, LOI, Pulse Width/T)]

(4)

The recommended setting for LOFA is LOR/16. Choosing a

larger value for LOFA increases T. Thus, for a given phase

difference between the LO input and the fREF input, the

instantaneous charge pump current is less than that available for

a LOFA value of LOR/16. Similarly, a smaller value for LOFA

decreases T, making more current available for the same phase

difference. In other words, a smaller value of LOFA enables the

synthesizer to settle faster in response to a frequency hop than a

large LOFA value. Take care to choose a value for LOFA that is

large enough (values greater than 4 are recommended) to

prevent the loop from oscillating back and forth in response to

a frequency hop.

Table 17. SPI Registers Associated with LO Synthesizer

Address (Hex)

Bit(s)

Width

Default Value

Name

0x00

[7:0]

0xFF

STBY

0x08

[5:0]

0x00

LOR [13:8]

0x09

[7:0]

0x38

LOR [7:0]

0x0A

[7:5]

0x5

LOA

[4:0]

0x00

LOB [12:8]

0x0B

[7:0]

0xiD

LOB [7:0]

0x0C

LOF

LOINV

[4:2]

0x00

LOI

[1:0]

0x00

LOTM

0x0D

[3:0]

0x00

LOFA [13:8]

0x0E

[7:0]

0x04

LOFA [7:0]

CLOCK SYNTHESIZER

The clock synthesizer is a fully programmable integer-N PLL

capable of supporting input clock and reference frequencies up

to 26 MHz. It is similar to the LO synthesizer described in

Figure 39 with the following exceptions:

•

It does not include an 8/9 prescaler nor an A counter.

•

It includes a negative-resistance core that, when used in

conjunction with an external LC tank and varactor, serves

as the VCO.

The 14-bit reference counter and 13-bit N-divider counter can

be programmed via the CKR and CKN registers. The clock

frequency, fCLK, is related to the reference frequency by the

equation

fCLK = (CKN/CKR × fREF)

(5)

The charge pump current is programmable via the CKI register

from 0.625 mA to 5.0 mA using the equation

IPUMP = (CKI + 1) × 0.625 mA

(6)

The fast acquire subcircuit of the charge pump is controlled

by the CKFA register in the same manner the LO synthesizer

is controlled by the LOFA register. An on-chip lock detect

function (enabled by the CKF bit) automatically increases the

output current for faster settling during channel changes. The

synthesizer may also be disabled using the CK standby bit

located in the STBY register.

AD9864BCPZ Datasheet(PDF) 27 Page - Analog Devices

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