AD9864-EBZ datasheet(19/48 Pages) AD

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AD9864

Data Sheet

Rev. A | Page 18 of 47

SERIAL PORT INTERFACE (SPI)

The serial port of the AD9864 has 3-wire or 4-wire SPI capability,

allowing read/write access to all registers that configure the internal

parameters of the device. The default 3-wire serial communication

port consists of a clock (PC), peripheral enable (PE), and

bidirectional data (PD) signal. The inputs to PC, PE, and PD

contain a Schmitt trigger with a nominal hysteresis of 0.4 V

centered about the digital interface supply, that is, VDDH/2.

A 4-wire SPI interface can be enabled by setting the MSB of the

SSICRB register (Register 0x19, Bit 7) and setting Register 0x3A

to 0x00, resulting in the output data appearing on only the

DOUTB pin with the PD pin functioning as an input pin only.

Note that because the default power-up state sets DOUTB low,

bus contention is possible for systems sharing the SPI output

line. To avoid any bus contention, the DOUTB pin can be three-

stated by setting the fourth control bit in the three-state bit

(Register 0x3B, Bit 3). This bit can then be toggled to gain

access to the shared SPI output line.

An 8-bit instruction header must accompany each read and

write SPI operation. Only the write operation supports an auto-

increment mode, which allows the entire chip to be configured

in a single write operation. The instruction header is shown in

Table 7. It includes a read/not-write indicator bit, six address

bits, and a Don’t Care bit. The data bits immediately follow the

instruction header for both read and write operations. Note that

the address and data are always given MSB first.

Table 7. Instruction Header Information

MSB

LSB

R/W

X = don’t care.

Figure 29 illustrates the timing requirements for a write

operation to the SPI port. After the peripheral enable (PE)

signal goes low, data (PD) pertaining to the instruction header

is read on the rising edges of the clock (PC). To initiate a write

operation, the read/not-write bit is set low. After the instruction

header is read, the eight data bits pertaining to the specified

the next eight clock cycles. PE stays low during the operation

and goes high at the end of the transfer. If PE rises before the

eight clock cycles have passed, the operation is aborted. If PE

stays low for an additional eight clock cycles, the destination

address is incremented and another eight bits of data are shifted

in. Again, if PE rises early, the current byte is ignored. By using

this implicit addressing mode, the chip can be configured with

a single write operation. Registers identified as being subject to

frequent updates, namely those associated with power control

and AGC operation, have been assigned adjacent addresses to

minimize the time required to update them. Note that multibyte

registers are big endian (the most significant byte has the lower

address) and are updated when a write to the least significant

byte occurs.

Figure 30 and Figure 31 illustrates the timing for 3-wire and

4-wire SPI read operations. Although the AD9864 does not

require read access for proper operation, it is often useful in the

product development phase or for system authentication. Note

that the readback enable bit (Register 0x3A, Bit 3) must be set

for a read operation with a 3-wire SPI interface. For 4-wire SPI

operation, this bit remains low (Register 0x3A = 0x00) but

DOUTB is enabled via the SSICRB register (Register 0x19, Bit 7).

Note that for the 4-wire SPI interface, the eight data bits appear

on the DOUTB pin with the same timing relationship as those

appearing at PD for 3-wire SPI interface case.

After the peripheral enable (PE) signal goes low, data (PD)

pertaining to the instruction header is read on the rising edges

of the clock (PC). A read operation occurs if the read/not-write

indicator is set high. After the address bits of the instruction

header are read, the eight data bits pertaining to the specified

of the next eight clock cycles. After the last data bit is shifted

out, the user must return PE high, causing PD to become three-

stated (for 3-wire case) and return to its normal status as an

input pin. Since the auto-increment mode is not supported for

read operations, an instruction header is required for each

initiating the next read operation.

tDS

tHI

tDH

tLOW

tCLK

R/W

A4 A0

D6 D1

DON'T

CARE

Figure 29. SPI Write Operation Timing

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