VIA Technologies, Inc.

Preliminary VT6304

11

Delay

4

R

0

Worse case repeater delay, expressed as 144+(delay*20)ns.

Link_active

1

rw

1

Link enabled. Default value of one subsequent to a power reset. Otherwise

cleared or set by software to control the value of the L bit transmitted in the

self-ID packet. The transmitted L bit shall be the logical AND of this bit and

the LPS signal.

Contender

1

rw

Pin

C/LKO

N

Contender. Cleared or set by software to control the value of the C bit

transmitted in the self-ID packet.

Pwr_class

3

rw

Pin

PC0-

PC2

Power class. Controls the value of the pwr field transmitted in the self-ID

packet.

000 - Node does not need power and does not repeat power

001 - Node is self-powered and provides a minimum of 15 W to the

bus

010 - Node is self-powered and provides a minimum of 30 W to the

bus.

011 - Node is self-powered and provides a minimum of 45 W to the

bus

100 - Node may be powered from the bus and is using up to 1 W.

101 - Node is powered from the bus and is using up to 1 W. An

additional 2 W is needed to enable the link and higher layers.

110 - Node is powered form the bus and is using up to 1 W. An

additional 5 W is needed to enable the link and higher layers.

111 - Node is powered from the bus and is using up to 1 W. An

additional 9 W is needed to enable the link and higher layers.

Jitter

3

R

0

The difference between the fastest and slowest repeater data delay, expressed

as (jitter+1)*20ns

Resume_int

1

Rw

0

Resume interrupt enable. When set to one, the PHY shall set port_event to

one if resume operations commence for any port.

ISBR

1

rw

0

Initiate short (arbitrated) bus reset. A write of one to this bit instructs the

PHY to arbitrate and issue a short bus reset. This bit is self-clearing.

Loop

1

rw

0

Loop detect. A write of one to this bit clears it to zero.

Pwr_fail

1

rw

0

Cable power failure detect. Set to one when the PS bit changes from one to

zero. A write of one to this bit clears it to zero.

Timeout

1

rw

0

Arbitration state machine timeout. A write of one to this bit clears it to zero.

Port_event

1

rw

0

Port event detect. The PHY sets this bit to one if any of connected, Bias,

Disabled or Fault change for a port whose Int_enable bit is one. The PHY

also sets this bit to one if resume operations commence for any port and

Resume_int is one. A write of one to this bit clears it to zero.

Enab_accel

1

rw

0

Enable arbitration acceleration. When set to one, the PHY shall use the

enhancements specification in P1394A.

Enab_multi

1

rw

0

Enable multi-speed packet concatenation. When set to one, the Link shall

signal the speed of all packets to the PHY.

Page_select

3

rw

000

Selects which of eight possible PHY register pages are accessible through

the window at PHY register address 1000b through 1111b, inclusive.

Port_select

4

rw

0000

If the page selected by Page_select presents per port information, this field

selects which port’s registers are accessible through the window at PHY