VIA Technologies, Inc.

Preliminary VT6304

12

register addressed 1000b through 1111b, inclusive.

The port Status page is used to access configuration and status information for each of the

PHY’s port. The port is selected by writing zero to Page_select and the desired port number

to Port_select in the PHY register at address 0111.

0

1

2

3

4

5

6

7

1000b

AStat

BStat

Child

connected

Bias

Disabled

1001b

Negotiated_speed

Int_enable

Fault

1010b

1011b

1100b

1101b

1110b

1111b

Size

Type

default

Description

Astat

2

r

-

TPA line State for the port

00 = invalid

01 =1

10 =0

11 =z

Bstat

2

r

-

(same encoding as Astat)

Child

1

r

-

If equal to one, the port is a child, else a parent. The meaning of this

bit is undefined from the time a bus reset is detected until the PHY

transitions to state T1:Child Handshake during the tree identify

process(see 4.4.2.2 in IEEE Std 1394-1995)

Conncted

1

r

0

If equal to one, the port is connected, else disconnected. The value

reported by this bit is filtered by hysteresis logic to reduce multiple

status changes caused by contact scrape when a connector is inserted

or removed.

Bias

1

r

-

If equal to one, bias voltage is detected( possible connection). The

value reported by this bit is filtered by hysteresis logic to reduce

multiple status changes caused by contact scrape when a connector is

inserted or removed.

Disabled

1

rw

0

When set to one, the port shall be disabled. The value of this bit

subsequent to a power reset is implementation-dependent, but should

be a strappable option.

Negotiated_sp

eed

3

r

-

Indicated the maximum speed negotiated between this PHY port and

its immediately connected port; the encoding is

000 – 98.304Mbit/s

001 - and 196.608 Mbit/s