It can be shown that this protection feature is vital to avoiding

overstress during overload and even under normal startup/

powerup.

Consider what happens if the output of a buck converter is at

zero volts with the maximum input voltage applied at the

input. This ’zero output volts’ condition represents the natural

initial condition at normal powerup/startup but could also be

a forced condition in the form of an output short. Then for the

LM1572, almost the full input of 16V can find iself across the

inductor during the on time of the switch. During the off time,

the voltage across the inductor reverses but the magnitude

of this voltage is only 0.5V (which comes from the ’typical’

Schottky forward drop).This leads to the problem: depite

having a ’current limit’, in fact there is absolutely no effective

current limit in this condition. Because if the switch turns on,

it has a minimum pulse width of about 300ns before it can

actually respond to any information about having exceeded

the current limit. This minimum pulse width is unavoidable

due to various internal delays, propagation intervals, and

also the internal blanking time carefully set for rejection of

transition noise, as required with current mode control.

Therefore using V=L*dI/dt is can be shown that for a switch-

ing frequency of 500kHz, and say with an inductance of

8.2µH, the current ramps up by about 0.58A during the

minimum switch on time of 0.3µs. During the off time of

1.7µs, it ramps down, but only by about 0.1A. Therefore the

current peak will incrementally increase or staircase up-

wards by a net 0.48A every cycle. And in a few cycles this

could blow the switch. Increasing the inductance will not

help, as it will only affect the rate of the current staircasing,

not necessarily its peak. In the absence of any other effec-

tive measure, the only way out in the current situation is to

’hope and pray’ that the the output voltage rises fast enough

before damage occurs. For a normal power up, the output

rail would rise eventually, at a rate which would be depen-

dent on the value of the output capacitance. However for a

short on the output, it would never rise. In either case we

have a potentially destructive situation. Now it can also be

shown that if the frequency was immediately reduced to

100kHz following the ’zero output volts’ condition, the off

time is increased to 10-0.3=9.7µs. This will cause the calcu-

lated current ramp-down to be 0.59A instead of 0.1A. Since

this is greater than the current ramp-up of 0.58A the current

will actually return to zero every cycle, and there will be no

staircasing. This is how the LM1572 frequency foldback

protection works, thus avoiding this potentially dangerous

condition altogether. We consider the two possible situations

for ’zero output volts condition’ in more detail below, to

understand it better.

By definition, an ’overload’ is where the switch current limit

has been reached, and then any attempt to increase the load

further, causes the output voltage rail to ’droop’, though the

load current remains virtually constant during this time. If an

attempt is made to increase the load even further, the volt-

age on the feedback pin will fall low enough to cause the

LM1572 to start lowering its switching frequency. At the

same time the output of the error amplifier clamps high (at

2V), and this causes the LM1572 to suddenly reduce the

on-time to the minimum pulse width. The foldback frequency

is now 100 kHz, and with this minimum pulse width, the

effective duty cycle is 3%. It can be easily shown by calcu-

lation that at the highest input voltage (worst case), assum-

ing a typical Schottky catch diode drop, a 3% duty cycle

produces a very low (almost zero) output voltage (ignoring

switch voltage drop here). However if the frequency had

remained at 500 kHz, the duty cycle would have been 15%,

and this would have led to a calculated output voltage of

(16*0.15)-0.5=2V, though we are forcing the output to zero.

This therefore represents a ’struggle’, which manifests itself

as an overstress condition. In this condition parasitics like

inductor winding resistance etc. will be called upon to control

the situation, and to stabilize the situation. For the lower

frequency case, with a duty cycle of 3%, since the calculated

output voltage is commensurate with the external condition

of a short-circuit on the output, the converter does not

’struggle’ to maintain this condition. However even with the

foldback protection as it is present on the LM1572, the

Designer is cautioned that the actual load current which can

flow with a short-circuit on the output, depends on various

factors. For example, high current Schottky diodes will be

found to lead to higher short-circuit currents than modestly

rated diodes. This is because it can be shown that if the

diode drop is lower than ’typical’ (as is the case for for high

current diodes), it requires a duty cycle even lower than 3%

to keep the calculated output voltage really close to ’zero’.

Therefore it may not be a good idea for example, to use say

a 5A/30V Schottky diode for a 1.5A application. The selected

diode in the typical application circuit is correctly sized to be

a 2A/30V Schottky from IRF.

Under startup, the frequency foldback effectively limits the

inrush current spike. The soft start feature, acting on its own,

cannot suppress the current spike at all. The role of softstart

is to gradually raise the duty cycle and thereby to bring up

the output rail slowly. But the inrush spike, which is mainly

the initial charging current of the output capacitors, occurs at

the moment of application of input power, even before the

voltage across the output capacitors has really started to rise

significantly. At this instant, soft start would call out for mini-

mum on time, but as seen above, this is just not enough to

limit the current. However, with foldback of frequency to

100kHz, the startup duty cycle falls from 15% to 3%. This

leaves enough off time for the current to subside every cycle,

as explained above, and there is no cumulative current

buildup, or ’staircasing’.

Layout Guidelines

Refer to the sample PCB layout provided. The Bill of Material

is also provided. The board is based on the schematic in

’Typical Applications’ for the fixed voltage part. The design is

based on the worked example presented in this datasheet.

The input voltage can vary between 8.5V to 16V. The output

rail is 5V and the peak current is 1.5A. The inductor is

however sized to handle only 1A continuous current. If

higher continuous rating is required (this depends on ambi-

ent temperature range too), an appropriately rated inductor,

possibly a higher series from the same vendor (keeping

inductance unchanged) can be selected.

Considering the critical aspects of the layout, it is recom-

mended that the routing and positioning of the 0.1µF input

decoupling capactor, C2, be kept the same as shown, and

also the catch diode D1. The rest are not critical, and may be

changed. Note however that the trace to the feedback pin is

routed through the quiet ground plane on the bottom side.

This helps prevent noise pickup and maintain correct output

voltage. Note that vias are provided, for example directly

below the IC to the ground plane, and this helps not only in

transferring heat to the other side of the board, but refer-

ences the IC ground directly to the ground plane.

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