AD7682BCPZ datasheet(8/35 Pages) AD

8 / 35 page

AD7682/AD7689

Data Sheet

Rev. H | Page 8 of 35

VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.

Table 5.

Parameter1

Symbol

Min

Typ

Max

Unit

CONVERSION TIME

tCONV

3.2

µs

CNV Rising Edge to Data Available

ACQUISITION TIME

tACQ

1.8

µs

TIME BETWEEN CONVERSIONS

tCYC

µs

DATA WRITE/READ DURING CONVERSION

tDATA

1.2

µs

SCK

Period

tSCK

tDSDO + 2

Low Time

tSCKL

High Time

tSCKH

Falling Edge to Data Remains Valid

tHSDO

Falling Edge to Data Valid Delay

tDSDO

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV

tEN

Pulse Width

tCNVH

Low to SDO D15 MSB Valid

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

High or Last SCK Falling Edge to SDO High Impedance

tDIS

Low to SCK Rising Edge

tCLSCK

DIN

Valid Setup Time from SCK Rising Edge

tSDIN

Valid Hold Time from SCK Rising Edge

tHDIN

See Figure 2 and Figure 3 for load conditions.

IOL

500µA

IOH

1.4V

TO SDO

50pF

Figure 2. Load Circuit for Digital Interface Timing

30% VIO

70% VIO

2V OR VIO – 0.5V1

0.8V OR 0.5V2

2V OR VIO – 0.5V1

tDELAY

12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.

20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 3. Voltage Levels for Timing

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