AD7682BCPZ datasheet(10/35 Pages) AD

10 / 35 page

AD7682/AD7689

Data Sheet

Rev. H | Page 10 of 35

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PAD IS NOT CONNECTED

INTERNALLY. FOR INCREASED

RELIABILITY OF THE SOLDER JOINTS, IT

IS RECOMMENDED THAT THE PAD BE

SOLDERED TO THE SYSTEM

GROUND PLANE.

SDO

15 VIO

SCK

DIN

11 CNV

VDD

REFIN

REF

GND

AD7682

TOP VIEW

(Not to Scale)

Figure 4. AD7682 LFCSP Pin Configuration

NOTES

1. THE EXPOSED PAD IS NOT CONNECTED

INTERNALLY. FOR INCREASED

RELIABILITY OF THE SOLDER JOINTS, IT

IS RECOMMENDED THAT THE PAD BE

SOLDERED TO THE SYSTEM

GROUND PLANE.

SDO

15 VIO

SCK

DIN

11 CNV

VDD

REFIN

REF

GND

AD7689

TOP VIEW

(Not to Scale)

Figure 5. AD7689 LFCSP Pin Configuration

Table 7. AD7682 LFCSP and AD7689 LFCSP Pin Function Descriptions

Pin No.

AD7682

LFCSP

Mnemonic

AD7689

LFCSP

Mnemonic

Type1

Description

1, 20

VDD

Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled

with 10 μF and 100 nF capacitors. When using the internal reference for a 2.5 V output,

the minimum must be 3.0 V. When using the internal reference for 4.096 V output, the

minimum must be 4.6 V.

REF

AI/O

Reference Input/Output. See the Voltage Reference Output/Input section. When the

internal reference is enabled, this pin produces a selectable system reference of 2.5 V or

4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a

buffered version of the voltage present on the REFIN pin (VDD − 0.5 V, maximum), which

is useful when using low cost, low power references. For improved drift performance,

connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin

needs decoupling with an external 10 μF capacitor connected as close to REF as possible.

See the Reference Decoupling section.

REFIN

AI/O

Internal Reference Output/Reference Buffer Input. See the Voltage Reference

Output/Input section. When using the internal reference, the internal unbuffered

reference voltage is present and requires decoupling with a 0.1 μF capacitor. When using

the internal reference buffer, apply a source between 0.5 V and (VDD − 0.5 V) that is

buffered to the REF pin, as described in the REF pin description.

4, 5

GND

Power Supply Ground.

IN4

No Connection (AD7682).

Analog Input Channel 4 (AD7689).

IN2

IN5

Analog Input Channel 2 (AD7682).

Analog Input Channel 5 (AD7689).

IN6

No Connection (AD7682).

Analog Input Channel 6 (AD7689).

IN3

IN7

Analog Input Channel 3 (AD7682).

Analog Input Channel 7 (AD7689).

COM

Common Channel Input. All input channels, IN[7:0], can be referenced to a common-

mode point of 0 V or VREF/2 V.

CNV

Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if

CNV is held low, the busy indictor is enabled.

DIN

Data Input. Use this input for writing to the 14-bit configuration register. The

configuration register can be written to during and after conversion.

SCK

Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data

on DIN in an MSB first fashion.

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