AD7682BCPZ datasheet(29/35 Pages) AD

29 / 35 page

Data Sheet

AD7682/AD7689

Rev. H | Page 29 of 35

GENERAL TIMING WITH A BUSY INDICATOR

Figure 40 details the timing for all three modes: RDC, RAC, and

RSC. Note that the gating item for both CFG and data readback

is at EOC. The data access must occur up to safe data

reading/writing time, tDATA. If the full CFG word is not written

to prior to EOC, it is discarded and the current configuration

remains.

At the EOC, if CNV is low, the busy indicator enables. In

addition, to generate the busy indicator properly, the host must

assert a minimum of 17 SCK falling edges to return SDO to

high impedance because the last bit on SDO remains active.

Unlike the case detailed in the Read/Write Spanning

Conversion Without a Busy Indicator section, if the conversion

result is not read out fully prior to EOC, the last bit clocked out

remains. If this bit is low, the busy signal indicator cannot be

generated because the busy generation requires either a high

impedance or a remaining bit high-to-low transition. A good

example of this occurs when an SPI host sends 16 SCKs because

these are usually limited to 8-bit or 16-bit bursts; therefore,

the LSB remains. Because the transition noise of the AD7682/

AD7689 is 4 LSBs peak-to-peak (or greater), the LSB is low 50%

of the time. For this interface, the SPI host needs to burst

24 SCKs, or a QSPI interface can be used and programmed for

17 SCKs.

The SCK can idle high or low depending on the CPOL and

CPHA settings if SPI is used. A simple solution is to use CPOL =

CPHA = 1 (not shown) with SCK idling high.

From power-up, in any read/write mode, the first three conver-

sion results are undefined because a valid CFG does not take

place until the second EOC; thus, two dummy conversions are

required. Also, if the state machine writes the CFG during the

power-up state (RDC shown), the CFG register needs to be

rewritten again at the next phase. The first valid data occurs in

phase (n + 1) when the CFG register is written during phase

(n − 1).

ACQUISITION

(n – 1) UNDEFINED

ACQUISITION

(n)

ACQUISITION

(n + 1)

ACQUISITION

(n + 2)

PHASE

POWER

EOC

START OF CONVERSION

(SOC)

EOC

CONVERSION

(n)

CONVERSION

(n + 1)

CONVERSION

(n – 2) UNDEFINED

tCONV

tCYC

tDATA

CNV

DIN

RDC

RAC

RSC

SDO

NOTES

1. CNV MUST BE LOW PRIOR TO THE END OF CONVERSION (EOC) TO GENERATE THE BUSY INDICATOR.

2. A TOTAL OF 17 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED,

A TOTAL OF 31 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.

DIN

SDO

DATA (n + 1)

DATA (n)

DATA (n + 1)

DIN

CFG (n)

CFG (n + 2)

CFG (n + 1)

CFG (n + 3)

SDO

SCK

n + 1

SCK

XXX

NOTE 1

NOTE 2

CFG (n)

CFG (n + 1)

CFG (n + 2)

CFG (n)

CFG (n + 1)

CFG (n + 2)

CFG (n + 3)

CONVERSION

(n – 1) UNDEFINED

Figure 40. General Interface Timing for the AD7682/AD7689 With a Busy Indicator

AD7682BCPZ Datasheet(PDF) 29 Page - Analog Devices

AD7682BCPZ Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Datasheet Download

Link URL