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Data Sheet

AD7984

SINGLE-TO-DIFFERENTIAL DRIVER

For applications using a single-ended analog signal, either

bipolar or unipolar, the ADA4941-x single-ended-to-

differential driver allows for a differential input into the part.

The schematic is shown in Figure 26.

R1 and R2 set the attenuation ratio between the input range and

the ADC range (VREF). R1, R2, and CF are chosen depending on

the desired input resistance, signal bandwidth, antialiasing, and

noise contribution. For example, for the ±10 V range with a 4 kΩ

impedance, R2 = 1 kΩ and R1 = 4 kΩ.

R3 and R4 set the common mode on the IN− input, and R5 and R6

set the common mode on the IN+ input of the ADC. The common

mode should be close to VREF/2. For example, for the ±10 V range

with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 = 10.5 kΩ,

and R6 = 9.76 kΩ.

Figure 26. Single-Ended-to-Differential Driver Circuit

VOLTAGE REFERENCE INPUT

The AD7984 voltage reference input, REF, has a dynamic input

impedance and should therefore be driven by a low impedance

source with efficient decoupling between the REF and GND

pins, as explained in the Layout section.

When REF is driven by a very low impedance source (for

example, a reference buffer using the AD8031 or the AD8605),

a 10 µF (X5R, 0805 size) ceramic chip capacitor is appropriate

for optimum performance.

If an unbuffered reference voltage is used, the decoupling value

depends on the reference used. For instance, a 22 µF (X5R,

1206 size) ceramic chip capacitor is appropriate for optimum

performance using a low temperature drift ADR43x reference.

If desired, a reference-decoupling capacitor with values as small

as 2.2 µF can be used with a minimal impact on performance,

especially DNL.

Regardless, there is no need for an additional lower value

ceramic decoupling capacitor (for example, 100 nF) between the

REF and GND pins.

POWER SUPPLY

The AD7984 uses two power supply pins: a core supply (VDD) and

a digital input/output interface supply (VIO). VIO allows direct

interface with any logic between 1.8 V and 5.5 V. To reduce the

number of supplies needed, VIO and VDD can be tied together.

The AD7984 is independent of power supply sequencing between

VIO and VDD. Additionally, it is very insensitive to power supply

variations over a wide frequency range, as shown in Figure 27.

Figure 27. PSRR vs. Frequency

15Ω

10µF

100nF

+2.5V

+5V REF

+5.2V

–0.2V

±10V,

±5V, ..

REF

VDD

GND

IN+

IN–

AD7984

2.7nF

ADA4941

OUTP

OUTN

REF

100nF

100

1000

FREQUENCY (kHz)

Rev. B | Page 15 of 24

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