AX88615 datasheet(10/26 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

CONFIDENTIAL

AX88615P 5-Port 10/100Mb Switch Controller

PRELIMINARY

2.4 Miscellaneous

Signal Name

Type Pin No.

Description

LCLK

Local Clock : 66Mhz. Used for system operation synchronous.

/RST

Reset : Active Low

The chip is reset when this signal is asserted Low.

REF_CLK

Reference clock : The input is a continue clock at 50Mhz for timing

reference with RMII interface.

/TEST

I/PU

Test Pin : Active LOW

The pin is just for test mode setting purpose only. Must be pull high when

normal operation.

MDIO

I/O

Station Management Data In/Out :

To read PHY Auto Negotiation Remote Capability register to get current

speed and duplex status. (See appendix also)

MDC

Station Management Data Clock Out : For MDIO reference clock.

DB_SEL[7:0]

I/PU

132-129,

119-116

Debug Mode Selection :

Enable debug selection when /TEST pin = 0

DB_OUT[7:0]

148-145,

124,123,

121,120

Debug Mode Monitor Output :

38,39,40,

56,57,73,

74,95,99,

100,102,

105-109,

125,126,

128,

150-156,

203-207

NC : Keep no connection

VDD

25, 48,

69, 92,

122, 144,

164, 195,

POWER : +3.3V +/-5%

VSS

8, 35,

67, 71,

83, 101,

112,115,

127, 139,

149, 157,

174,185,

208

POWER: 0V

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