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DS3142 Datasheet(PDF) 32 Page - Dallas Semiconductor |
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DS3142 Datasheet(HTML) 32 Page - Dallas Semiconductor |
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32 / 88 page  DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers 32 of 88 7.7 DS3/E3 Framer 7.7.1 DS3/E3 Framer Register Description Table 7-D. DS3/E3 Framer Register Map ADDR REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 10 T3E3CR1 E3SnC1 E3SnC0 T3IDLE TRAI TAIS TPT CBEN DS3M 11 T3E3CR2 FRESYNC N/A TFEBE AFEBED ECC FECC1 FECC0 E3CVE 12 T3E3EIC MEIMS FBEIC1 FBEIC0 FBEI T3CPBEI T3PBEI EXZI BPVI 18 T3E3SR N/A N/A SEF T3IDLE RAI AIS OOF LOS 19 T3E3SRL COFAL N/A SEFL T3IDLEL RAIL AISL OOFL LOSL 1A T3E3SRIE COFAIE N/A SEFIE T3IDLEIE RAIIE AISIE OOFIE LOSIE 1B T3E3IR RUA1 T3AIC E3Sn N/A EXZL MBEL FBEL ZSCDL 20 BPVCR1 BPV7 BPV6 BPV5 BPV4 BPV3 BPV2 BPV1 BPV0 21 BPVCR2 BPV15 BPV14 BPV13 BPV12 BPV11 BPV10 BPV9 BPV8 22 EXZCR1 EXZ7 EXZ6 EXZ5 EXZ4 EXZ3 EXZ2 EXZ1 EXZ0 23 EXZCR2 EXZ15 EXZ14 EXZ13 EXZ12 EXZ11 EXZ10 EXZ9 EXZ8 24 FECR1 FE7 FE6 FE5 FE4 FE3 FE2 FE1 FE0 25 FECR2 FE15 FE14 FE13 FE12 FE11 FE10 FE9 FE8 26 PCR1 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 27 PCR2 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 28 CPCR1 CPE7 CPE6 CPE5 CPE4 CPE3 CPE2 CPE1 CPE0 29 CPCR2 CPE15 CPE14 CPE13 CPE12 CPE11 CPE10 CPE9 CPE8 2A FEBECR1 FEBE7 FEBE6 FEBE5 FEBE4 FEBE3 FEBE2 FEBE1 FEBE0 2B FEBECR2 FEBE15 FEBE14 FEBE13 FEBE12 FEBE11 FEBE10 FEBE9 FEBE8 Register Name: T3E3CR1 Register Description: T3/E3 Control Register Register Address: 10h Bit # 7 6 5 4 3 2 1 0 Name E3SnC1 E3SnC0 T3IDLE TRAI TAIS TPT CBEN DS3M Default 0 0 0 0 0 0 0 0 Bit 0: DS3 Mode Select (DS3M). Selects DS3 or E3 operation. It must be set immediately after reset to select DS3 mode. 0 = E3 mode 1 = DS3 mode Bit 1: C-Bit Parity Mode Enable (CBEN). This bit is only active when the framer is in DS3 mode. When this bit is logic 0, C-Bit Parity is defeated and the C bits are sourced from the TDAT input pin. 0 = disable C-Bit Parity mode (also known as the M23 mode) 1 = enable C-Bit Parity mode Bit 2: DS3/E3 Transmit Pass-Through Enable (TPT). When this bit is set to logic 1, the transmit formatter sources data from the TDAT input on every TCLK cycle and does not insert framing overhead into the transmit data stream. In this mode the TDEN/TGCLK output still marks where the payload bits would be if TPT were not enabled, and the TSOF output still marks the start of a frame. When in this mode, the BERT does not function in payload- only mode; entire-frame mode should be used instead. 0 = configure the formatter to insert framing overhead bits 1 = configure the formatter to pass through TDAT data without inserting framing overhead bits |
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