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Data Sheet

AD7265

Rev. B | Page 5 of 28

TIMING SPECIFICATIONS

AVDD = DVDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, internal/external reference = 2.5 V, TA = TMAX to TMIN, unless otherwise noted1.

Table 2.

Parameter

Limit at TMIN, TMAX

Unit

Description

fSCLK2

MHz min

TA = −40°C to +85°C

MHz min

TA > 85°C to 125°C

MHz max

tCONVERT

14 × tSCLK

ns max

tSCLK = 1/fSCLK

875

ns max

fSCLK = 16 MHz

tQUIET

ns min

Minimum time between end of serial read and next falling edge of CS

15/20

ns min

VDD = 5 V/3 V, CS to SCLK setup time, TA = −40°C to +85°C

20/30

ns min

VDD = 5 V/3 V, CS to SCLK setup time, TA > 85°C to 125°C

ns max

Delay from CS until DOUTA and DOUTB are three-state disabled

t4 3

ns max

Data access time after SCLK falling edge, VDD = 3 V

ns max

Data access time after SCLK falling edge, VDD = 5 V

0.45 tSCLK

ns min

SCLK low pulse width

0.45 tSCLK

ns min

SCLK high pulse width

ns min

SCLK to data valid hold time, VDD = 3 V

ns min

SCLK to data valid hold time, VDD = 5 V

ns max

CS rising edge to DOUTA, DOUTB, high impedance

ns min

CS rising edge to falling edge pulse width

t10

ns min

SCLK falling edge to DOUTA, DOUTB, high impedance

ns max

SCLK falling edge to DOUTA, DOUTB, high impedance

1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Serial

Interface section and Figure 41 and Figure 42.

2 Minimum SCLK for specified performance; with slower SCLK frequencies, performance specifications apply typically.

3 The time required for the output to cross 0.4 V or 2.4 V.

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